Hardware-software architecture for priority queue management in real-time and embedded systems

Abstract

The use of hardware-based data structures for accelerating real-time and embedded system applications is limited by the scarceness of hardware resources. Being limited by the silicon area available, hardware data structures cannot scale in size as easily as their software counterparts. We assert a hardware-software co-design approach is required to elegantly overcome these limitations. In this paper, we present a hybrid priority queue architecture that includes a hardware accelerated binary heap that can also be managed in software when the queue size exceeds hardware limits. A memory mapped interface provides software with access to priority-queue structured on-chip memory, which enables quick and low overhead transitions between hardware and software management. As an application of this hybrid architecture, we present a scalable task scheduler for real-time systems that reduces scheduler processing overhead and improves timing determinism of the scheduler.

The Construction of a Precise Agricultural Information System Based on Internet of Things

“…It can achieve a variety of heterogeneous network interfaces, has a wide range of network access capabilities, and can meet the requirements of management for intelligent gateways. By contrast, the rapid development of an embedded system facilitates the easy modification of the system's software and hardware [21][22][23]. It has prominent portability and can be customized based on actual demands.…”

Hardware architecture support for mixed criticality and real-time systems

“…• A hardware accelerated binary min heap design is presented, which supports enqueue and peek operations in O(1) time, returns the top-priority element in O(1) time, and completes a dequeue operation in O(log n) time. [44] • A scalable hardware-software priority queue architecture that enables fast and low-overhead transitions of queue management between hardware and hybrid software-hardware modes of operation is proposed and evaluated. [44] In Chapter 4, a hybrid software-hardware scheduler architecture that reduces scheduling overhead and improves predictability is presented.…”

“…[44] • A scalable hardware-software priority queue architecture that enables fast and low-overhead transitions of queue management between hardware and hybrid software-hardware modes of operation is proposed and evaluated. [44] In Chapter 4, a hybrid software-hardware scheduler architecture that reduces scheduling overhead and improves predictability is presented. [44] In Chapter 6:…”

“…[44] In Chapter 4, a hybrid software-hardware scheduler architecture that reduces scheduling overhead and improves predictability is presented. [44] In Chapter 6:…”

Design and implementation of an FPGA-based piecewise affine Kalman Filter for Cyber-Physical Systems

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