Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

Ismael, Sarmad F.; Tareq, Omar; Qassim, Yahya T.

doi:10.11591/ijece.v9i1.pp148-156

Cited by 8 publications

(6 citation statements)

References 11 publications

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“…However, this solution increases the sequential execution and costs more calculations in each thread. Many researches have been proposed to parallelize the Bresenham algorithm [4], but their solution lacks for physical hardware or their implementation deals with small data set [6]. Indeed, we exploited the benefits of parallelization in efficient implementation,wherethe problem that can be divided into independent sub-problems is more suitable.Thereby, we prefer the (DDA) algorithm for the implementation on GPU.…”

Section: Gpu-based Line Segment Algorithmmentioning

confidence: 99%

“…The voxelization is accomplished using a 3D scan conversion to generate a discrete surface of a voxelizedobject; it differs from scan conversion that concerns with filling 2D triangles or 2D projection of 3D triangles [2], their algorithms are more abundance in literature than a 3D scan conversion. Therefore we will focus on explaining 3D scan conversion only.In such processes the speed is required in generatingvoxels; some researches accelerated the operation using the standard Bresenham algorithm that has been adopted for a long time [3], [4], [5] and [6]. While other researches tried to use other algorithms like DDA [7], [8]and [9].…”

Section: Introductionmentioning

confidence: 99%

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Voxelization Parallelism Using CUDA Architecture

Alrawy¹,

Ali²

2020

(AREJ)

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The voxelization process is an essential stage in three dimensional (3D) graphics pipeline. Its implementation should precede displaying objects in the pipeline. In this paper, different Voxelization algorithms are modified and parallelized to accelerate the operation of this stage. The 3D Digital Differential Analyzer (DDA) algorithm is used for line voxelization. This algorithm is utilized in triangle filling using the scan-line and the edge-function algorithms. The first one is designed to produce lines in parallel while the second can produce voxels. All these algorithms are parallelized using CUDA architecture and implemented on GPU processor. The actual implementation of these algorithms is examined and optimized according to the occupancy and block size metrics. The experimental results show that the acceleration amount of 3D DDA was about 4352x max compared to the OpenGL implementation, and the edge function implementation has been executed at a higher speed than the scan-line for object triangles voxelization.

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Section: Gpu-based Line Segment Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Voxelization Parallelism Using CUDA Architecture

Alrawy¹,

Ali²

2020

(AREJ)

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“…These results include the performance of the 3D rendering operations which is based on off-axis technique to create stereo pairs and Bresenham's line drawing algorithm to draw objects, which have been implemented on FPGA hardware. Also, researchers in [9], improved an approach to speed up the Bresenham algorithm by partitioning each line into a number of segments, finding the points belong to those segments, and then formulating the overall line by drawing them simultaneously. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only.…”

Section: Introductionmentioning

confidence: 99%

Hardware accelerator for anti-aliasing Wu's line algorithm using FPGA

Younis

2021

TELKOMNIKA

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Digital images are suffering from the stair-step effect because they are built from small pixels. This effect termes aliasing and the method uses to decrease so-called anti-aliasing. This paper offers a hardware accelerator of an antialiasing algorithm using HLS (high level synthesis) along straight-line segments or edges. These straight-line segments are smoothed by modifying the intensity of the pixel. The hardware implementation of two different architectures which is based on Zynq FPGA are presented in this work. The first architecture is built from one core while the second architecture is built from multi-core and uses a parallel technique to speed up the algorithm by dividing line segments into sub-segments and drawing them after smoothing instantaneously to formulate the main line. This parallel usage leads to a very fast execution of Wu's algorithm which is represented one-tenth hardware runtime for one core only. Also, the optimized resource utilization and power consumption for different cores have been compared, through single-core design which utilizes 8% and consumes 1.6 W, while utilized resources using 10 cores are 77% with a power consumption of 2 W.

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“…Knowledge about the lines in an image is useful in many applications such as unmanned vehicle guidance, robot navigation, medical image processing, object recognition, computer vision and artificial intelligence [1][2][3][4][5][6][7][8][9][10][11][12]. In a high-resolution image, thousands of lines in different angles are possible.…”

Section: Introductionmentioning

confidence: 99%

A Fast-Efficient parallel processing algorithm for straight line detection

Rasiq¹,

Jeevan²,

Krishnakumar³

2019

IJEECS

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<p>This work presents a novel method for detecting straight lines in an image at a very high speed with optimum number of processors and their functionalities. The method can be used to extract straight lines directly from an image without noise removal and pre-processing. First the square image is converted to a binary edge image using a parallel edge detection mechanism. The parallel edge detection mechanism used in this work is capable of producing edge image within a short time. Then the binary square image is transferred to a system having large number of Processing Elements (PEs). A PE has only limited jobs such as pixel scanning, compare line length with nearby PEs and transmit data to the Main Control Unit (MCU). The MCU collects data from all PEs and evaluates straight lines. Even if the number of PEs is high, it is comparatively very much less than the parallel Hough Transform method and practically implementable using recent ULSI technologies.</p>

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Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

Cited by 8 publications

References 11 publications

Voxelization Parallelism Using CUDA Architecture

Voxelization Parallelism Using CUDA Architecture

Hardware accelerator for anti-aliasing Wu's line algorithm using FPGA

A Fast-Efficient parallel processing algorithm for straight line detection

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