Hardware-software co-design of G729 voice encoder using Virtex-II Pro<sup>TM</sup>FPGA

ACELP is a type of voice coder algorithm that compresses speech signal based on model parameters of human voice. This paper presents two methods for design and implementation of ACELP vocoder. One is fully hardware design, it is characterized by pipelining and parallel operation of functional units, and it has been tested on an FPGA; the other is hardware-software co-design, it is characterized by dividing the algorithm into hardware part and software part, and it has been tested with NIOS II and FPGA. Experiments' results show that fully hardware implementation can achieve faster speed and smaller latency, and co-design owns shorter design cycle and better voice quality.

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“…According to [8], three obvious factors lead us to the partitioning reason. The first factor is to find parallel blocks.…”

Section: B Hardware/software Partitionmentioning

confidence: 99%

“…Some researchers try to implement the voice coder algorithm with FPGA, but it is too time exhausting and because of limited area of FPGA's, it is not suitable for multi channel application. In recent years, hardware-software codesign has caused public's attention [8].…”

Section: Introductionmentioning

confidence: 99%

Two methods of design and implementation of ACELP vocoder

Zhao

Zhang

Lin

2013

2013 IEEE International Conference on Signal Processing, Communication and Computing (ICSPCC 2013)

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“…The results of the experiment show that the co-design implementation reduced the latency of the algorithm. [12] stated that the use of the hardware-software partitioning approach resulted in an 88.23μs time saving, while each function implemented was approximately 190 times faster when implemented in hardware than when implemented in software. [12] did not state the latencies of the encoder and decoder of this CS-ACELP speech compression algorithm implementation.…”

Section: Review Of Existing Researchmentioning

confidence: 99%

Open-Loop Pitch Analysis for the Conjugate-Structure Algebraic-Code-Excited Linear -Prediction Speech Compression Algorithm

Tomar¹,

L²

2011

AJMAHS

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Voice-over Internet Protocol (VoIP) telephony which is the transmission of real-time voice over an internet protocol (IP) data network, is increasingly becoming a variant telecommunication technology that one day may surpass the old analog and digital telephone systems. The Quality-of-Service (QoS) factor is an important parameter to be considered when measuring the performance of a VoIP system. Algorithmic delay (latency) may influence the QoS of a VoIP system. This paper presents the hardware implementation of the Open-Loop Pitch Analysis component of the Conjugate-Structure Algebraic-Code-Excited Linear-Prediction (CS-ACELP) speech compression algorithms. The Open-Loop Pitch Analysis units were implemented in hardware using Xilinx 11.1 ISE, after which ITU-T test vectors were used to determine whether they were equivalent implementations of the Open-Loop Pitch Analysis. The algorithmic delays of hardware-implementations were obtained via simulation using Modelsim XE 6.4b while the algorithmic delays of the software-implemented speech compression algorithms were obtained by software profiling using the GPROF profiler.After comparison the algorithmic delays of the hardware-implementations of the Open-Loop Pitch Analysis was found to be shorter than the algorithmic delays of their software-implemented and hardware-implemented counterparts.

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