Hardware/software co-testing of embedded memories in complex SOCs

Fang, Bai Hong; Xu, Qian; Nicolici, N.

doi:10.1109/iccad.2003.1257872

Cited by 2 publications

(2 citation statements)

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“…The embedded processor can be found on virtually in any SoC, and reusing the processor for BIST to reduce the area overhead. Processor based BIST and BISR are not a new concept [7,8]. But, to the best of our knowledge there is no processor based embedded flash memory testing available in the published literature.…”

Section: Testing Of Embedded Flash Memorymentioning

confidence: 99%

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Built-in self-test for flash memory embedded in SoC

Banerjee

Chowdhury

2006

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)

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Flash memories are a type of non-volatile memory, which are becoming more and more popular for System-on-Chip. But, flash memories are suffered by different types of disturb faults. In the present paper, some new disturb faults that may appear in flash memory are proposed. A modifies March algorithm is developed to detect these faults. Finally, an embedded processor-based Built-In Self-Test (BIST) design is implemented for embedded memories. The proposed method utilizes the concept of reusing the processor in SoC environment. By reusing the embedded processor, the area overhead due to BIST can be reduced to a great extent. The area overhead is only due to the circuits required to design memory wrapper cell. The experimental results show that the area overhead due to BIST is less than % for a typical flash memory.

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Section: Testing Of Embedded Flash Memorymentioning

confidence: 99%

“…It needs only a low cost ATE to initialize the tests and to analyze final results. In [7], authors described a new BIST method, called hardware/software co-testing for testing embedded memories. However, BIST may introduces excessive power dissipation during testing and area overhead.…”

Section: Introductionmentioning

confidence: 99%