Hardware-software implementation of HEVC decoder on Zynq

Ayadi, Lella Aicha; Loukil, Hassen; Ayed, Mohamed Ali Ben; Nouri, Mohammad

doi:10.1007/s11042-019-08548-3

Cited by 2 publications

(3 citation statements)

References 22 publications

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“…Decoding of the newest VVC standard was demonstrated at high throughput on consumer CPUs [150,166]. A co-processing implementation by Ayadi et al [12] was able to reach 4K@60FPS on a high-end Zyng-7045 embedded platform by utilizing both the CPU and FPGA parts which makes it possibly the most lightweight solution for high-throughput HEVC compression covered in this survey.…”

Section: Summary Of Reviewed Implementationsmentioning

confidence: 96%

“…The authors saved 49ś52% of the encoding time at a 0.60ś0.88% BD-Rate increase. Another acceleration strategy is to oload the full inter prediction step, or a part of it, to a GPU [53,58,134] or an FPGA [10,12]. A comprehensive review by Zhang et al [164] covers literature on inter prediction of HEVC up to the year 2019.…”

Section: Computational Complexity Analysismentioning

confidence: 99%

“…In [11,12], Ayadi et al proposed an FPGA-accelerated HEVC decoder on a Zynq SoC platform. Based on the decoding time distribution of the reference decoder running on an ARM processor, the authors determined the calculation of interpolation ilters during motion compensation to be the most computationally expensive part and implemented this function on the FPGA part of the Zynq board.…”

Section: Inter-frame Compressionmentioning

confidence: 99%

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Image and Video Coding Techniques for Ultra-low Latency

et al. 2022

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The next generation of wireless networks fosters the adoption of latency-critical applications such as XR, connected industry, or autonomous driving. This survey gathers implementation aspects of different image and video coding schemes and discusses their tradeoffs. Standardized video coding technologies such as HEVC or VVC provide a high compression ratio, but their enormous complexity sets the scene for alternative approaches like still image, mezzanine, or texture compression in scenarios with tight resource or latency constraints. Regardless of the coding scheme, we found inter-device memory transfers and the lack of sub-frame coding as limitations of current full-system and software-programmable implementations.

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Section: Summary Of Reviewed Implementationsmentioning

confidence: 96%

Section: Computational Complexity Analysismentioning

confidence: 99%

Section: Inter-frame Compressionmentioning

confidence: 99%

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Image and Video Coding Techniques for Ultra-low Latency

et al. 2022

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Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

Touzani

Mansouri

Errahimi

et al. 2021

Circuit Theory & Apps

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Summary Statistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%).

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Hardware-software implementation of HEVC decoder on Zynq

Cited by 2 publications

References 22 publications

Image and Video Coding Techniques for Ultra-low Latency

Image and Video Coding Techniques for Ultra-low Latency

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

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