Hardware/Software Interface for Multi-Dimensional Processor Arrays

Darte, Alain; Derrien, Steven; Risset, Tanguy

doi:10.1109/asap.2005.38

Cited by 3 publications

(2 citation statements)

References 19 publications

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“…Systolic arrays are examples of such data-flow IPs but they are not the only ones. In this paper we only target linear array of processor which have a small number of input/output ports, the problem of interfacing 2D array of processors has been studied in [7], but the problems encountered are quite different and many IP integrated to SoC are 1D arrays because of the high bandwidth required by 2D arrays.…”

Section: Introductionmentioning

confidence: 99%

Master Interface for On-chip Hardware Accelerator Burst Communications

Fraboulet¹,

Risset

2007

J VLSI Sign Process Syst Sign Im

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We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. Then we measure the throughput obtained for different architectures of the interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow IP. We show in which configuration the optimal communication scheme can be reached.

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Section: Introductionmentioning

confidence: 99%

Master Interface for On-chip Hardware Accelerator Burst Communications

Fraboulet¹,

Risset

2007

J VLSI Sign Process Syst Sign Im

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“…Darte et al [10,9] address the problem of finding a tight linear schedule after tiling and clustering (LSGP) the virtual processor space. However, the problem of finding a good cluster shape is not addressed, i.e., the number of dimensions to cluster, and the choice of those dimensions.…”

Section: Related Workmentioning

confidence: 99%

Automatic mapping of nested loops to FPGAS

Bondhugula

Ramanujam

Sadayappan

2007

Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

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This paper present a framework for automatic mapping of perfectly nested loops with constant dependences onto regular processor arrays, suitable for direct implementation on Field Programmable Gate Arrays (FPGAs). The problem is modeled as that of finding a suitable completion procedure for a full-rank linear transformation on the iteration space. The approach enables extraction of necessary degrees of communication-free and pipelined parallelism to optimize performance under the resource constraints of limited logic resources and I/O bandwidth available on an FPGA. The generation of control signals for the custom processing elements is also addressed. Examples of automatic derivation of parallel designs for some common nested loops are provided. Experimental results on the Cray XD1 show that an FPGA-based matrix-multiplication design obtained using the framework attains significant speedup on the XD1's attached FPGA, when compared to execution on the XD1 CPU.

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