Hardware/Software Partitioning for Heterogeneous Multicore SoC Using Genetic Algorithm

Luo, Li; He, Hui; Dou, Qi; Xu, Weiya

doi:10.1109/isdea.2012.501

Cited by 7 publications

(5 citation statements)

References 10 publications

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“…The rule of partition suppose that the module where spend more time will be considered as hardware component and the module where spend less time will be considered as software parts [18]. Then, we find the result shown in figure 8 based on the native execution of the fingerprint recognition on a 6 Giga Byte memory, 2.2 GHz frequency of the processor Intel Core i3 with Windows 7 as operating system.…”

Section: Step 1: Partitioningmentioning

confidence: 99%

An Accelerated Architecture Based on GPU and Multi-Processor Design for Fingerprint Recognition

Ayed¹,

Elkosantini²

2016

ijacsa

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Abstract-Fingerprint recognition is widely used in security systems to recognize humans. In both industry and scientific literature, many fingerprint identification systems were developed using different techniques and approaches. Although the number of conducted research works in this field, developed systems suffer for some limitations partially those related the real time computation and fingerprint recognition. Accordingly, this paper proposes a reliable algorithm for fingerprint recognition based on the extraction and matching of Minutiae. In this paper, we present also an accelerated architecture based on GPU and multi-processor design in which the suggested fingerprint recognition algorithm is implemented.

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Section: Step 1: Partitioningmentioning

confidence: 99%

An Accelerated Architecture Based on GPU and Multi-Processor Design for Fingerprint Recognition

Ayed¹,

Elkosantini²

2016

ijacsa

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“…generate unnecessary cache upgrades [11] and inflict additional overheads to the system [12]. Serialized coding bottlenecks are present less paralleled multithreading application threads, which is a likely cause of CPU pipeline halt [13].…”

Section: Main Contributionsmentioning

confidence: 99%

“…In the asymmetrical designs the similar optimizing approach cannot be applied to all processing blocks as they are different. In [11] Li et al had explored the feasibility of genetic algorithm in a heterogeneous multi-core architecture with NoC (Network-on-Chip) Communication structures.…”

Section: Parallelism and Multi-core Processorsmentioning

confidence: 99%

“…DEDICATED scheme is applicable to allocate threads requesting to perform writing action to dedicated CPU cores [11].…”

Section: Power Dissipation Problem Categorizationmentioning

confidence: 99%

“…11 shows a native Android system under the governor of Completely Fair Scheduler (CFS)[150], which allocates the time slices for a series of multithreaded user interactive applications. In Android system, apps are scheduled by the underlying Linux kernel scheduler, and in Android 4.0 the Linux kernel used is Completely Fair Scheduler (CFS).…”

mentioning

confidence: 99%

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Usage-pattern-based scheduling schemes for power optimization in multi-core systems

Hou¹

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This thesis discusses the scheduling schemes with app usage pattern awareness for power dissipation optimization in mobile multi-core computing systems. The power dissipation of mobile multi-core computing systems becomes crucial as the power wall symptom arises. One way to resolve the power wall issue is to manage the system resource with power awareness focus. Three main areas of work are presented in the thesis to address the power dissipation issues.First, three scheduling schemes are proposed to decompose the instantaneous power dissipation into different components to model the redundancies in application inflicted power dissipation. The decomposition identifies the manageable power components as the Thread Interference Power which exists among the context switching of multithreading applications. Different amounts of Thread Interference Power dissipate between different combinations of adjacent threads. In this thesis the application combination and power dissipation relationship is studied, identified at system runtime. Application thread scheduling schemes are designed based on the assumption that the usage pattern of a mobile system user is periodical, hence the future application sequence and possible power dissipation are predictable based on the past performance recorded.The scheduling schemes presenting in the thesis make scheduling decisions based on the instantaneous system application combinations and the possible incoming application predicted. The scheduler reorders the application threads according to the amount of Thread Interference Power dissipated. The scheduler is testified in a simulated environment built with GEM5 and McPAT. The simulation results show that the adoption of usage pattern aware scheduling method is capable of reducing the total system power dissipation up to 19% compared to the total system power dissipated without applying the proposed method.To incorporate the proposed scheduling schemes in a Linux scheduler, the quantization method of the Thread Interference Power dissipation with system monitored performance events is studied. Multiple power dissipation related problems are studied to generalize the function of the scheduling schemes as functions of a scheduler. Mutual cache evictions or invalidations by parallel processes, corresponding data movements, context switching overheads and code serialization bottlenecks due to unfortunate scheduled synchronization / locking mechanisms on shared access resources are major contributors to the excessive computing power dissipation of modern chip multiprocessor (CMP) architectures. The proposed Linux scheduler manages above mentioned problems based on user-specific application usage pattern identified in the Thread Interference Power model. To extend the scheduling capacity of the proposed scheduler, novel Dynamic Voltage and Frequency Scaling (DVFS) techniques are developed for ARM asymmetrical System-on-Chip (SoC) designs and tested in a three clustered CPU setup. The result of the proposed scheduler shows a maximum of 22.2%...

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An Improved Blind Optimization Algorithm for Hardware/Software Partitioning and Scheduling

Zhao

Zhang

et al. 2018

Lecture Notes in Computer Science

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Hardware/Software Partitioning for Heterogeneous Multicore SoC Using Genetic Algorithm

Cited by 7 publications

References 10 publications

An Accelerated Architecture Based on GPU and Multi-Processor Design for Fingerprint Recognition

An Accelerated Architecture Based on GPU and Multi-Processor Design for Fingerprint Recognition

Usage-pattern-based scheduling schemes for power optimization in multi-core systems

An Improved Blind Optimization Algorithm for Hardware/Software Partitioning and Scheduling

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