Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)
DOI: 10.1109/iccd.1999.808609
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Hardware/software partitioning of multirate system using static scheduling theory

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Cited by 1 publication
(2 citation statements)
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“…This technique is valuable if aperiodic tasks have strict response times but can lead to very costly design if the tasks are rarely launched or if their execution is not critical. In [21] aperiodic tasks are not included but the multirate issue is considered in the context of a monoprocessor HW / SW architecture. The method is based on the fixed priority scheduling theory [14,16], however the design space exploration is limited to a fine grain solution (processor + coprocessor) or separately to a coarse grain architecture which include a processor and parametrized ASIC.The dependence question is solved while using the Inverse Deadline technique, but like in [3] the question of dependent tasks with distinct periods is not considered (for instance the issue of tasks release time).…”
Section: State Of the Artmentioning
confidence: 99%
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“…This technique is valuable if aperiodic tasks have strict response times but can lead to very costly design if the tasks are rarely launched or if their execution is not critical. In [21] aperiodic tasks are not included but the multirate issue is considered in the context of a monoprocessor HW / SW architecture. The method is based on the fixed priority scheduling theory [14,16], however the design space exploration is limited to a fine grain solution (processor + coprocessor) or separately to a coarse grain architecture which include a processor and parametrized ASIC.The dependence question is solved while using the Inverse Deadline technique, but like in [3] the question of dependent tasks with distinct periods is not considered (for instance the issue of tasks release time).…”
Section: State Of the Artmentioning
confidence: 99%
“…Three kinds of architectures are usually targeted, the first one is based on monoprocessor architectures with hardware accelerators which can [21,2] or not run simultaneously [20]. The second one addresses multiprocessor architectures [23,5,22] and the last one includes ASIP [7,12] designs.…”
Section: State Of the Artmentioning
confidence: 99%