Hardware solution for implementing the entire inverse IDCTs in HEVC decoder

Nayeri, Hamid Reza; Zargari, Farzad

doi:10.1080/00207217.2018.1440427

Cited by 1 publication

(2 citation statements)

References 12 publications

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“…When the PEO4 module outputs the results to BF4, the BF4 module begins calculating the addition and subtraction as per Eqs. (21) and (22). In the following eight cycles, the PEO8 module calculates the matrix product C 8o Z 8o and the BF4 module simultaneously outputs the results.…”

Section: Data Flow Of the Proposed Idctmentioning

confidence: 99%

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A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

Chen

Liu

2020

EURASIP J. Adv. Signal Process.

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In this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

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Section: Data Flow Of the Proposed Idctmentioning

confidence: 99%

“…Based on this buffer, the 32-pixel transform unit can achieve a frequency of 400 MHz for a 65-nm process. The resource-sharing pipelined architecture [21] is synthesized by using Nan-Gate OpenPDK 45 nm library achieving a 222-MHz clock rate and supporting real-time decoding of 4096 × 3072 video sequences with 70 fps.…”

Section: Introductionmentioning

confidence: 99%

A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

Chen

Liu

2020

EURASIP J. Adv. Signal Process.

View full text Add to dashboard Cite

show abstract

Hardware solution for implementing the entire inverse IDCTs in HEVC decoder

Cited by 1 publication

References 12 publications

A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

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