Hardware support for accurate per-task energy metering in multicore systems

Liu, Qixiao; Moretó, Miquel; Jiménez, Víctor; Abella, Jaume; Cazorla, Francisco J.; Valero, Mateo

doi:10.1145/2555289.2555291

Cited by 5 publications

(12 citation statements)

References 11 publications

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“…Details about the configuration can be found in Table 4. Other parameters are analogous to those in [5].…”

Section: Methodsmentioning

confidence: 99%

“…However, both approaches cannot take into account the impact of inter-task interferences unless appropriate solutions provide accurate per-task energy metering in multicores. Our work in [5] provides Per-Task Energy Metering (PTEM) for on-chip resources (cores, caches, etc.). Our proposal in this paper, DReAM, provides such support for DRAM memories.…”

Section: Background and Related Workmentioning

confidence: 99%

“…As in [5], the time the OS spends working on behalf of a given task is attributed to the calling task. The remaining energy consumed by the OS can be evenly attributed to all running tasks.…”

Section: Putting All Togethermentioning

confidence: 99%

“…Further, different tasks incur different power consumption: e.g., 25.7W (482.sphinx3) versus 40.4W (462.libquantum). However, while per-task energy metering solutions exist for processors [5], to the best of our knowledge, no mechanism exists to accurately measure the per-task memory energy consumption in multicore systems.…”

Section: Introductionmentioning

confidence: 99%

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DReAM: Per-Task DRAM Energy Metering in Multicore Systems

Liu

Moretó

Abella

et al. 2014

Lecture Notes in Computer Science

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Abstract. Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate pertask DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, such as per-task energy-aware task scheduling and energy-aware billing in datacenters. In particular, the contributions of this paper are (i) an ideal per-task energy metering model for DRAM memories; (ii) DReAM, an accurate, yet low cost, implementation of the ideal model (less than 5% accuracy error when 16 tasks share memory); and (iii) a comparison with standard methods (even distribution and access-count based) proving that DReAM is more accurate than these other methods.

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“…Details about the configuration can be found in Table 4. Other parameters are analogous to those in [5].…”

Section: Methodsmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

Section: Putting All Togethermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

DReAM: Per-Task DRAM Energy Metering in Multicore Systems

Liu

Moretó

Abella

et al. 2014

Lecture Notes in Computer Science

Self Cite

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“…RELATED WORK Performance Monitoring Counters (PMCs) have been traditionally used to measure average performance and power consumption [28]. One of the few works that addresses contention monitoring between tasks is [43], which uses cache scouts to monitor contention on shared caches.…”

Section: B Fpga Evaluationmentioning

confidence: 99%

Contention-aware performance monitoring counter support for real-time MPSoCs

Jalle

Fernandez

Abella

et al. 2016

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)

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Abstract-Tasks running in MPSoCs experience contention delays when accessing MPSoC's shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task suffers due to other corunning tasks, and the particular hardware shared resources in which contention occurs, is of prominent importance to increase confidence on derived execution time bounds of tasks. And, whenever those bounds are violated, ACD provides information on the reasons for overruns. Unfortunately, existing MPSoC designs considered in real-time domains offer limited hardware support to measure tasks' ACD losing all these potential benefits. In this paper we propose the Contention Cycle Stack (CCS), a mechanism that extends performance monitoring counters to track specific events that allow estimating the ACD that each task suffers from every contending task on every hardware shared resource. We build the CCS using a set of specialized low-overhead Performance Monitoring Counters for the Cobham Gaisler GR740 (NGMP) MPSoC -used in the space domain -for which we show CCS's benefits.

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Cross Architectural Power Modelling

Chen

Kilpatrick

Nikolopoulos

et al. 2020

2020 20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGRID)

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Existing power modelling research focuses on the model rather than the process for developing models. An automated power modelling process that can be deployed on different processors for developing power models with high accuracy is developed. For this, (i) an automated hardware performance counter selection method that selects counters best correlated to power on both ARM and Intel processors, (ii) a noise filter based on clustering that can reduce the mean error in power models, and (iii) a two stage power model that surmounts challenges in using existing power models across multiple architectures are proposed and developed. The key results are: (i) the automated hardware performance counter selection method achieves comparable selection to the manual method reported in the literature, (ii) the noise filter reduces the mean error in power models by up to 55%, and (iii) the two stage power model can predict dynamic power with less than 8% error on both ARM and Intel processors, which is an improvement over classic models.Index Terms-power modelling, cross architecture, hardware counters, noise filtering.

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Hardware support for accurate per-task energy metering in multicore systems

Cited by 5 publications

References 11 publications

DReAM: Per-Task DRAM Energy Metering in Multicore Systems

DReAM: Per-Task DRAM Energy Metering in Multicore Systems

Contention-aware performance monitoring counter support for real-time MPSoCs

Cross Architectural Power Modelling

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