Hardware Support for Embedded Java

Schoeberl, Martin

doi:10.1007/978-1-4419-8158-5_7

Cited by 3 publications

(2 citation statements)

References 52 publications

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“…For Nazomi JA108 [15], previously known as JSTAR, a Java co-processor sits between the native processor and the memory subsystem. JA108 fetches Java bytecodes from memory and translates them into native microprocessor instructions.…”

Section: Dedicated Bytecode Processor and Co-processormentioning

confidence: 99%

Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension

Thongkaew

Isshiki

et al. 2015

Journal of Information Processing

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The Dalvik virtual machine (Dalvik VM) is an essential piece of software that runs applications on the Android operating system. Android application programs are commonly written in the Java language and compiled to Java bytecode. The Java bytecode is converted to Dalvik bytecode (Dalvik Executable file) which is interpreted by the Dalvik VM on typical Android devices. The significant disadvantage of interpretation is a much slower speed of program execution compared to direct machine code execution on the host CPU. However, there are many techniques to improve the performance of Dalvik VM. A typical methodology is just-in-time compilation which converts frequently executed sequences of interpreted instruction to host machine code. Other methodologies include dedicated bytecode processors and architectural extension on existing processors. In this paper, we propose an alternative methodology, "Fetch & Decode Hardware Extension," to improve the performance of Dalvik VM. The Fetch & Decode Hardware Extension is a specially designed hardware component to fetch and decode Dalvik bytecode directly, while the core computations within the virtual registers are done by the optimized Dalvik bytecode software handler. The experimental results show the speed improvements on Arithmetic instructions, loop & conditional instructions and method invocation & return instructions, can be achieved up to 2.4x, 2.7x and 1.8x, respectively. The approximate size of the proposed hardware extension is 0.03 mm 2 (equivalent to 10.56 Kgate) and consumes additional power of only 0.23 mW. The stated results are obtained from logic synthesis using the TSMC 90 nm technology @ 200 MHz clock frequency.

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Section: Dedicated Bytecode Processor and Co-processormentioning

confidence: 99%

Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension

Thongkaew

Isshiki

et al. 2015

Journal of Information Processing

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“…6 Currently, since the JVM specification does not mandate any particular host OS or host platform (Radhakrishnan et al, 2001), there are implementations that emulate the JVM on a wide range of platforms and devices (Gough and Corney, 2000;Lindholm et al, 2012) as embedded systems (Levis and Culler, 2002;Koshy and Pandey, 2005;Simon and Cifuentes, 2005;Simon et al, 2006;Aslam et al, 2008;Brandner et al, 2009;Thomm et al, 2010), smart-card devices (Guthery, 1997;Oestreicher, 1999;Azevedo et al, 2005), desktops (Haase and Guy, 2007), and servers (Downey, 2007), to name a few. Furthermore, apart from the conventional pure software implementations, the JVM design allow for a variety of implementation choices ranging from pure hardware (Hardin, 2001;Berekovic et al, 1997;O'Connor and Tremblay, 1997;McGhan and O'Connor, 1998;Tan et al, 2006;Puffitsch and Schoeberl, 2007;Schoeberl, 2012) as well as a combination of hardware and software (i.e., hardware and software co-design implementations) (Fong et al, 2012).…”

Section: A Primer On the Jvm And Its Key Runtime Datamentioning

confidence: 99%

Toward harnessing a Java high-level language virtual machine for supporting software testing

Durelli¹

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H i g h-l e v e l language virtual machines (HLL VMs) have been playing a key role as a mechanism for implementing programming languages. Languages that run on these execution environments have many advantages over languages that are compiled to native code. These advantages have led HLL VMs to gain broad acceptance in both academy and industry. However, much of the research in this area has been devoted to boosting the performance of these execution environments. Few efforts have attempted to introduce features that automate or facilitate some software engineering activities, including software testing. This research argues that HLL VMs provide a reasonable basis for building an integrated software testing environment. To this end, two software testing features that build on the characteristics of a Java virtual machine (JVM) were devised. The purpose of the first feature is to automate weak mutation. Augmented with mutation support, the chosen JVM achieved speedups of as much as 95% in comparison to a strong mutation tool. To support the testing of concurrent programs, the second feature is concerned with enabling the deterministic re-execution of Java programs and exploration of new scheduling sequences.

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Noc-HMP

Salčić

Park

Teich

et al. 2017

ACM Trans. Des. Autom. Electron. Syst.

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Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article presents a NoC-based Heterogeneous Multi-Processor system, called NoC-HMP, which is a scalable platform for embedded systems developed in the GALS language SystemJ. NoC-HMP uses a time-predictable TDMA-MIN NoC to guarantee latencies and communication time between the two types of time-predictable cores and can be customized for a specific performance goal through the execution strategy and scheduling of SystemJ program deployed across multiple cores. Examples of different execution strategies are introduced, explored and analyzed via measurements. The number of used cores can be minimized to achieve the target performance of the application. TDMA-MIN allows easy extensions of NoC-HMP with other cores or IP blocks. Experiments show a significant improvement of performance over a single core system and demonstrate how the addition of cores affects the performance of the designed system.

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Hardware Support for Embedded Java

Cited by 3 publications

References 52 publications

Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension

Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension

Toward harnessing a Java high-level language virtual machine for supporting software testing

Noc-HMP

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