Hardware support for UNUM floating point arithmetic

Bocco, Andrea; Durand, Yves; Dinechin, Florent de

doi:10.1109/prime.2017.7974115

Cited by 10 publications

(11 citation statements)

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“…This addressing mode is only suitable for strictly sequential access and doesn't allow, for instance, in-place updates of the array. For such situations, SMURF provides 1 ○. In 1 ○ and 2 ○ the empty boxes (m) represent the unused bits in memory.…”

Section: Main Memory Organization Of Unum Array Elementsmentioning

confidence: 99%

“…For such situations, SMURF provides 1 ○. In 1 ○ and 2 ○ the empty boxes (m) represent the unused bits in memory. Although 2 ○ wastes fewer bits than 1 ○, it may not fully utilize the memory.…”

Section: Main Memory Organization Of Unum Array Elementsmentioning

confidence: 99%

“…According to our experiments, FP algorithms which need precision are iterative. They generally tend to increase the length of their variables, thus in the end, the initially unused space in 1 ○ is eventually used.…”

Section: Main Memory Organization Of Unum Array Elementsmentioning

confidence: 99%

“…In 1 ○, the control unit 5 ○ decodes the input instruction and generates the control words for the decode and execute stages. 1 ○ hosts the gbound Register File 6 ○ (gRF, Section 3). The gRF has two read ports, one write port and hosts 32 Variable Precision (VP) gbounds with normalized mantissas.…”

Section: Smurf Micro-architecture Hardware Implementationmentioning

confidence: 99%

“…Only few UNUM type I hardware demonstrators have been built (e.g. [1], [8], [5]) but none of them support multiple UE illustrate how to efficiently store numbers in main memory.…”

Section: Introductionmentioning

confidence: 99%

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Smurf

Bocco

Durand

Dinechin

2019

Proceedings of the Conference for Next Generation Arithmetic 2019

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This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost. CCS CONCEPTS • Hardware → Emerging technologies; Very large scale integration design; Communication hardware, interfaces and storage; Power and energy; • Computer systems organization → Architectures; Embedded and cyber-physical systems; • Computing methodologies → Modeling and simulation;

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Section: Main Memory Organization Of Unum Array Elementsmentioning

confidence: 99%

Section: Main Memory Organization Of Unum Array Elementsmentioning

confidence: 99%

Section: Main Memory Organization Of Unum Array Elementsmentioning

confidence: 99%

Section: Smurf Micro-architecture Hardware Implementationmentioning

confidence: 99%

“…Only few UNUM type I hardware demonstrators have been built (e.g. [1], [8], [5]) but none of them support multiple UE illustrate how to efficiently store numbers in main memory.…”

Section: Introductionmentioning

confidence: 99%

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