Hardware support for WCET analysis of hard real-time multicore systems

Paolieri, Marco; Quiñones, Eduardo; Cazorla, Francisco J.; Bernat, Guillem; Valero, Mateo

doi:10.1145/1555754.1555764

Cited by 178 publications

(193 citation statements)

References 9 publications

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“…However, the priority of each device is fixed, which means that it cannot be dynamically allocated as tasks change. So the timeliness of real-time tasks are not guaranteed to be satisfied [13,18].…”

Section: Previous Workmentioning

confidence: 99%

Hard real-time bus architecture and arbitration algorithm based on AMBA

Ding

2015

2015 International Conference on Information and Communications Technologies (ICT 2015)

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Real-time processors are growly used in embedded applications. Considering that the time cost in data transfer among devices is much more than the time used for computation and operation, it's important to design a high-speed real-time bus structure in real-time systems. This paper offers a deep investigation to the characteristics of real-time systems as well as the basic structure of real-time processors and real-time buses. We designed a high-speed and time-predictable bus architecture called RTBus, where high-performance AXI protocol is employed. To accurately calculate the bus access time for master devices, a two-level real-time bus arbitration algorithm, which adopts the warning-line judgment mechanism and simulated annealing algorithm, is proposed for the operation of the RTBus. Finally, it is proved that RTBus provides a good solution to the conflicts when sharing resources in real-time processors.

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Section: Previous Workmentioning

confidence: 99%

Hard real-time bus architecture and arbitration algorithm based on AMBA

Ding

2015

2015 International Conference on Information and Communications Technologies (ICT 2015)

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“…We also implemented ticket locks with the F&I primitive, but with focus on assuring fairness between HRT threads without requiring a specific bus arbitration. In [5] Molesky et al present an arbitration for a bus, the Deferred Bus theorem, which is the baseline for the bus arbitration we are using to assure fairness of spin locks [6]. Molesky et al show that their Deferred Bus enables synchronisation mechanisms for mutual exclusion with linear waiting, and bounded semaphores for predictable synchronisation in multiprocessor real-time systems.…”

Section: Related Workmentioning

confidence: 99%

“…Interferences are Overview of our multi-core processor, stressing the embedded hardware synchronisation primitives in the real-time memory controller. handled by an upper bounding of accesses to shared resources like a real-time capable bus [6] as interconnect to memory and cores, as well as a real-time capable memory controller. As local memories we use scratchpad memories for each core, namely a data scratchpad (DSP) and a dynamic instruction scratchpad (D-ISP) [13], but no caches for the HRT threads.…”

Section: Hard Real-time Capable Synchronisation Techniquesmentioning

confidence: 99%

“…The RTOS uses a TAS spin lock for critical sections inside the mutex lock. We can assure fairness and progress of the used spin lock by specific arbitration strategies in the real-time bus [6]. Additionally, a linked list contains all waiting HRT threads in FIFO ordering to guarantee fairness, that is the longest waiting thread wakes up and acquires the mutex lock when the previous holding HRT thread releases it.…”

Section: Sw Synchronisation Hw Primitive Strategymentioning

confidence: 99%

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Time analysable synchronisation techniques for parallelised hard real-time applications

Gerdes¹,

Ungerer²,

Rochange³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In this paper we present synchronisation techniques for hard real-time (HRT) capable execution of parallelised applications on embedded multi-core processors. We show how commonly used software synchronisation techniques can be implemented in a time analysable way based on the proposed hardware primitives. We choose to implement the hardware synchronisation primitives in the memory controller for two reasons. Firstly, we remove pessimism in the WCET analysis of parallelised HRT applications. Secondly, we enable that the implementation of synchronisation techniques is mostly independent of the chosen instruction set architecture (ISA) which allows to use the existing ISAs without enhancements. We analyse the presented synchronisation techniques with the static worstcase execution time (WCET) analysis tool OTAWA. In summary, our specifically engineered synchronisation techniques yield a tremendous gain on the WCET of parallelised HRT applications. I. INTRODUCTIONFor a long time research in parallel applications and architectures was bound to the domain of high-performance computing. With the upcoming of multi-core processors, parallelisation became also important in other domains, namely desktop end-user systems and embedded systems as well. However, embedded systems have different needs and must fulfil other requirements than high-performance systems. Today's HRT applications in the automotive, avionic or machinery industry are executed on single-core processors. The new trend of using multi-cores in safety-critical domains sparks off research on running HRT tasks in parallel with other tasks to execute mixed-critical application workloads. Our research goes even one step further: we target multi-core execution of parallelised HRT tasks without sacrificing timing guarantees.In this paper, we focus on the timing predictability of synchronisation in parallelised HRT applications using the static WCET analysis tool OTAWA [1]. The contributions of this paper are as follows: we show that specifically engineered software synchronisation techniques, busy-waiting as well as blocking synchronisation methods, are timing analysable. We assess these synchronisation primitives and their hardware respectively software implementation with respect to their impact on the WCET, and the possible gain for the WCET of parallelised HRT applications.The presented synchronisation techniques can be implemented independently of the ISA, as the logic for the hardware synchronisation primitives is nested in the memory controller.

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“…It guarantees that the memory access latencies for a particular core remain independent from the memory requests by the other cores. Thus, latencies can be bounded and included in WCET estimates [1].…”

Section: Introductionmentioning

confidence: 99%

MBBA: A Multi-Bandwidth Bus Arbiter for Hard Real-Time

Bourgade¹,

Rochange²,

Michiel³

et al. 2010

2010 5th International Conference on Embedded and Multimedia Computing

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Multi-core architectures are being increasingly used in embedded systems as they offer several advantages: improved hardware integration, low thermal dissipation and reduced energy consumption, while they make it possible to improve the computing power. In order to run real-time software on a multicore architecture, computing the Worst-Case Execution Time of every thread should be achievable. This notably involves bounding memory latencies by employing a predictable bus arbiter. However, state-of-the-art techniques prove to be irrelevant to schedule unbalanced workloads in which some threads require more bus bandwidth than the other ones. This paper proposes a new bus arbitration scheme that ensures that the shared bus latencies can be upper bounded. Compared to other schemes that make the bus latencies predictable, like the Round-Robin protocol, our approach defines several levels of bandwidth to meet requirements that may vary from one thread to another. Experimental results (WCET estimates) show that the worstcase bus latency is noticeably shortened, compared to RoundRobin, for the cores with highest priority that get the largest bandwidth. The relevance of the scheme is shown through an example workload composed of various benchmarks.

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Hardware support for WCET analysis of hard real-time multicore systems

Cited by 178 publications

References 9 publications

Hard real-time bus architecture and arbitration algorithm based on AMBA

Hard real-time bus architecture and arbitration algorithm based on AMBA

Time analysable synchronisation techniques for parallelised hard real-time applications

MBBA: A Multi-Bandwidth Bus Arbiter for Hard Real-Time

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