Hardware trojan attacks in FPGA devices

Mal-Sarkar, Sanchita; Krishna, Aswin; Ghosh, Anandaroop; Bhunia, Swarup

doi:10.1145/2591513.2591520

Cited by 43 publications

(2 citation statements)

References 7 publications

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“…Mal-Sarkar [10] and Jacob [11] demonstrated that thirdparty IPs can allow attacks such as hardware Trojans and malware that can be launched within any device using the compromised IP. A use case is to compromise a SoC running a secure update.…”

Section: Background and Related Workmentioning

confidence: 99%

Secured-by-design systems-on-chip: a MBSE Approach

Milan,

Lagadec,

Bollengier

et al. 2023

Proceedings of the 34th International Workshop on Rapid System Prototyping

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Section: Background and Related Workmentioning

confidence: 99%

Secured-by-design systems-on-chip: a MBSE Approach

Milan,

Lagadec,

Bollengier

et al. 2023

Proceedings of the 34th International Workshop on Rapid System Prototyping

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“…OneofthemainsecurityissuesfacedbyanAESacceleratoronFPGAsthatareusedincloud environmentisthesecurityofsecretkeyusedforencryptioninsidetheFPGA (Trimberger&Moore, 2014). Several types of hardware Trojans are being inserted into the accelerator by attackers for leakingthesecretkey.TheTrojanscanbeinsertedindifferentphasesinacceleratorcreationsuch asdesign,integration,testing,andbitstreamtransfer.Generally,itisdifficulttofindaTrojanorthe triggeringconditionofaTrojanbecausetheTrojancircuitwilldisguiseasafunctionalcircuitthat isnecessaryforthedesign.Poweranalysis,comparingthedesignwithagoldenone(Trojan-free design),andsoonarethemainmethodsusedtofindaTrojaninadesign.Ifthereisakey-leaking Trojan,thenittakesmorepowerthanusual (Bhasin,Danger,Guilley,Ngo,&Sauvage,2013;Jin& Makris,2010;Johnson,Saha,Chakraborty,Mukhopadhyay,&Gören,2014).DetectingaTrojanina designthroughpoweranalysisisdifficultbecausetofindthetriggeringconditionistimeconsuming andneedtocheckwithalargenumberoftestinputs.Comparingwithagoldendesignislessefficient asthereisaneedtostoremorethantwogoldendesigns (Mal-Sarkar,Krishna,Ghosh,&Bhunia, 2014;Mal-Sarkar,Karametal.,2016).…”

Section: Introductionmentioning

confidence: 99%

Securing AES Accelerator from Key-Leaking Trojans on FPGA

Ramasubramanian

2020

International Journal of Embedded and Real-Time Communication Systems

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Reconfigurable hardware presents a useful platform for building systems with high performance and a secured nature. A new method for protecting 128-bit AES accelerator on FPGA for embedded systems and cloud servers is proposed. One of the major issues faced by the AES accelerator is the security of the key stored inside the FPGA memory. The article proposes a masking scheme which makes the secret key unidentifiable. With the new method of masking scheme, there is no way for an attacker to leak and identify the secret key from the working device through undetected hardware unit. To work with the masked key, a modified key expansion that maintains the throughput through a properly designed multistage pipelining is proposed. The proposed method takes the advantage of reconfigurable computing for flexible and provides security against key-leaking Trojans. The efficiency of the masked AES implementation is found to be 28.5 Mbps, which is 17.87% higher than the existing best wok. The security of the proposed masked scheme is validated through correlation and hamming distance.

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Reversing a Lattice ECP3 FPGA for Bitstream Protection

Celebucki

Graham

Gunawardena

2018

Critical Infrastructure Protection XII

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Hardware trojan attacks in FPGA devices

Cited by 43 publications

References 7 publications

Secured-by-design systems-on-chip: a MBSE Approach

Secured-by-design systems-on-chip: a MBSE Approach

Securing AES Accelerator from Key-Leaking Trojans on FPGA

Reversing a Lattice ECP3 FPGA for Bitstream Protection

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