Hardwired Control Unit Implementation for a 16-Bit Risc Processor Using Verilog

Abstract

RISC processor mostly uses hardwired control unit. The hardwired control unit should generate the appropriate control signals for each instruction in the 16-bit RISC processor. To interpret instructions and produce control signals, the control unit utilizes fixed logic circuits. The Processor is divided into various sections, including the datapath , control path, and memory components. The control unit is required to create control signals in order for Datapath to work. The hardwired control units are designed using combinational logic and Sequential logic circuits. This approach can result in faster execution times and lower power consumption. Different types of processors use hardwired control unit because of increased throughput which is critical for high-performance computing systems. This paper presents an implementation of a hardwired control unit of a 16-bit RISC processor. The control unit contains different modules such as the instruction register, decoder, sequence counter, and control logic gate, which are developed using Verilog. Finally, the process is created by putting together various modules and then testing it through extensive simulation with the help of Xilinx ISE software.