HARE: History-Aware Adaptive Routing Algorithm for Endpoint Congestion in Networks-on-Chip

Jin, Kang; Li, Cunlu; Dong, Dezun; Fu, Binzhang

doi:10.1007/s10766-018-0614-6

Cited by 15 publications

(6 citation statements)

References 26 publications

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“…Adaptive routing. To assess the efficacy of adaptive routing against NoC clogging, we implement and evaluate the DyXY [45], Footprint [22], and HARE [37] adaptive routing schemes. Figure 7 compares GPU performance with the adaptive policies to our baseline which uses CDR routing [3].…”

Section: B Noc-centric Approachesmentioning

confidence: 99%

“…Cache-centric approaches (e.g., [5], [13], [28], [29], [30], [31]) rely solely on inter-core locality, but are fundamentally limited as they either (i) incur the complexity and overhead of precisely tracking sharers for correctness (either at the level of a cache block [5], [28] or across memory regions as in coarse-grain coherence [13]); (ii) deliver suboptimal effective bandwidth to applications with (large) shared data sets (as in shared L1 caches [29], [30]); or (iii) must search for potential sharers (as in Realistic Probing (RP) [31]). In contrast, NoC-centric approaches (e.g., [22], [33], [37], [45]) attempt to address clogging through (selective) overprovisioning or advanced network policies. Within the NoC, performance is fundamentally constrained by the clogged links and can only be improved by providing more bandwidth.…”

Section: Introductionmentioning

confidence: 99%

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Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures

Zhao

Eeckhout

Jahre

2022

2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

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Heterogeneous architectures with latency-sensitive CPU cores and bandwidth-intensive accelerators are attractive as they deliver high performance at favorable cost. These architectures typically have significantly more compute cores than memory nodes. The many bandwidth-intensive accelerators hence overwhelm the few memory nodes, resulting in suboptimal accelerator performance -as their bandwidth needs are not met -and poor CPU performance -because memory node blocking creates high latencies. We call this phenomenon network clogging. Since network clogging is a widespread issue in heterogeneous architectures, we first investigate if existing state-of-the-art approaches can address it. We find that the most effective prior approach, called Realistic Probing (RP), is suboptimal because it searches the local caches of other cores for missing data.We propose Delegated Replies which lets memory nodes speculatively delegate the responsibility of replying to last-level cache hits to the private cache that last accessed the requested cache block, hence avoiding the search that fundamentally limits RP. Moreover, Delegated Replies uses the (typically) under-utilized request network for delegation; it is the reply network links of the memory nodes that commonly clog because replies include complete cache blocks in addition to metadata. We evaluate Delegated Replies in the context of heterogeneous architectures with latency-sensitive CPU cores and bandwidthintensive GPU cores and find that it improves GPU (CPU) performance by 14.2% (5.2%) and 25.7% (8.8%) on average compared to RP and our baseline, respectively.

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Section: B Noc-centric Approachesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures

Zhao

Eeckhout

Jahre

2022

2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

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“…This phenomenon reduces the effective rate of the NoC, or in the worst case, can cause blocking of traffic and failure of certain network resources. For this purpose, a huge number of approaches were proposed to surmount the negative effect of congestion and improve the network performance: reconfigurable routers and novel NoC architectures were designed to avoid router and network congestion; congestion metrics were included to complete the design of adaptive routing algorithms intended for congestion reduction [14,6,28]; End-to-end flow control technique also was suggested to adjust injecting packets into any emerging network congestion [30,26,27]; thus selection strategies were developed to reduce congestion and improve network performance with regards to latency [1,8,15].…”

Section: Our Graphical Simulator For Data-flow Monitoring On Networmentioning

confidence: 99%

Novel Metric for Load Balance and Congestion Reducing in Network on-Chip

Aroui

Benyamina

Boulet

et al. 2020

SCPE

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The Network-on-Chip (NoC) is an alternative pattern that is considered as an emerging technology for distributed embedded systems. The traditional use of multi-cores in computing increase the calculation performance; but affect the network communication causing congestion on nodes which therefore decrease the global performance of the NoC. To alleviate this problematic phenomenon, several strategies were implemented, to reduce or prevent the occurrence of congestion, such as network status metrics, new routing algorithm, packets injection control, and switching strategies. In this paper, we carried out a study on congestion in a 2D mesh network, through various detailed simulations. Our focus was on the most used congestion metrics in NoC. According to our experiments and performed simulations under different traffic scenarios, we found that these metrics are less representative, less significant and yet they do not give a true overview of reading within the NoC nodes at a given cycle. Our study shows that the use of other complementary information regarding the state of nodes and network traffic flow in the design of a novel metric, can really improve the results. In this paper, we put forward a novel metric that takes into account the overall operating state of a router in the design of adaptive XY routing algorithm, aiming to improve routing decisions and network performance. We compare the throughput, latency, resource utilization, and congestion occurrence of proposed metric to three published metrics on two specific traffic patterns in a varied packets injection rate. Our results indicate that our novel metric-based adaptive XY routing has overcome congestion and significantly improve resource utilization through load balancing; achieving an average improvement rate up to 40 compared to adaptive XY routing based on the previous congestion metrics.

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“…End congestion due to HoL blocking is one of the main reasons for performance degradation in IQR [12]. The traditional IQRs have input queues organized as VCs [13].…”

Section: Introductionmentioning

confidence: 99%

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

2021

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Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged in a particular order in each Virtual Channel (VC). This implementation is vulnerable to HoL blocking, as the switch allocator can allocate only those packets which are available at the head in a VC. In this paper, Swapped Buffer (SB) Router architecture is proposed to schedule packets in input buffers by using SB registers. The VCs are designed as SBs, this allows the packets stored in SB registers along with the head packet of VC to participate in SA. The concept of the SB register minimizes the conflicts in SA and thus reduces HoL blocking, therefore improves the performance of NoC. This paper proposes a priority mechanism to prioritize the non-head packets as compared to head packets in case of conflict between them. Two methods have been proposed in this paper, to enhance the performance of the NoC router. First, a VC allocation technique is proposed to optimize the order of packets in the input buffer. Next, SB-Router is combined with the Fill VC allocation technique to further enhance the performance of NoC routers. The performance of the proposed router is evaluated and the experimental results indicate that our design achieves latency improvement of 68.75% over (Time-Series) TS-Router for uniform traffic at the injection rate of 0.42 flits/cycle for a 64 node mesh network with moderate power consumption and area usage. The performance improvement in packet latency for traces from Princeton Application Repository for Shared-Memory Computers (PARSEC) has also been evaluated. With the achieved reduction in latency, the proposed method has the potential to serve high-speed operations while mapping different applications on multiple core architectures.

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HARE: History-Aware Adaptive Routing Algorithm for Endpoint Congestion in Networks-on-Chip

Cited by 15 publications

References 26 publications

Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures

Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures

Novel Metric for Load Balance and Congestion Reducing in Network on-Chip

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

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