Harnessing voltage margins for energy efficiency in multicore CPUs

On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study

“…Exposing the safe voltage margins of an application is a time-consuming and difficult process due to several abnormal behaviors that can exist [52], [53], [54], [55]. To this end, we developed an automated characterization framework, which is outlined in Figure 5, (1) to identify the target system's limits when it operates at scaled voltage, frequency conditions and DRAM refresh rates, and (2) to record/log the effects of a program's execution under these conditions.…”

“…The automated framework (outlined in Figure 5) is easily configurable by the user and can be embedded to any Linux-based system, with similar voltage and frequency regulation capabilities. The characterization framework [52], [53] consists of three phases (Initialization, Execution, Parsing). During the initialization phase, a user can declare a benchmark list with corresponding input datasets to run in any desirable characterization setup.…”

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

“…We experimentally obtain the Vmin values of the 10 SPEC CPU2006 [10] benchmark on the three X-Gene 2 chips (TTT, TFF, TSS) [11], running the entire time-consuming undervolting experiment ten times for each benchmark, following the flow described in Section 3.A. This part of our study focuses on a quantitative analysis of the safe Vmin for diverse chips of the same architecture in order to expose the potential guardbands of each chip, as well as to quantify how the program behavior affects the guardband and to measure the core-to-core and chip-to-chip variation.…”

“…To achieve this, we can train a workload dependent prediction model considering also performance counters as we recently proposed in [11]. Such a model can take also into consideration the history of voltage droops occurred over time.…”

Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories

“…However, in real-world applications, these voltage margins are unnecessarily conservative and eliminating them can directly deliver significant power and energy efficiency. In recent years, it has been shown that aggressive undervolting, i.e., supply voltage underscaling below the standard nominal level can substantially improve the energy efficiency of real hardware including CPUs [1], [2], [3], [4], [5], [6], GPUs [7], ASICs [8], DRAMs [9], and SRAMs [10]. This paper extends the aggressive undervolting approach for commercial FPGAs.…”