Hazard checking in pipelined processor designs using symbolic model checking

Schönherr, Jens; Schreiber, I.; Fordran, Eva; Straube, Bernd

doi:10.1109/eurmic.1999.794450

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2017

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Cited by 2 publications

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“…Jiajing Lu designed a dynamic scheduling algorithm to improve the pipeline efficiency, which only increases one singleinstruction buffer and some combination logic [4]. Also, Schönherr J, Schreiber I, and Fordran E proposed a method using symbolic model checking to detect hazards in pipelined processor [5].…”

Section: Introductionmentioning

confidence: 99%

A Method to Detect Hazards in Pipeline Processor

Han

Jiang

et al. 2017

MATEC Web Conf.

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Abstract. In order to improve the throughput of the processors, pipeline technique is widely used to implement the instruction-level parallelism. However, this technique also leads to data hazards which has a great influence on the performance. This paper proposed a method called supply-matching to detect and solve data hazards efficiently. The logic of bypassing and stalling can be easily realized through this method. Furthermore, an RTL description of instructions was also introduced in this paper to reduce resource utilization. The case study was conducted through a five-stage microprocessor based on the PowerPC architecture with different approaches. Experiment results show our method requires less resources and achieves better performance.

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Section: Introductionmentioning

confidence: 99%