HC-FFT: highly configurable and efficient FFT implementation on FPGA

Abstract

FFT is one of the basic building blocks in many applications such as sensors, radars, communications. For some applications, e.g., real-time spectral monitoring and analysis, FFT needs to be "run-time configurable" so that the system is real-time. When examining the previous work on configurable real-time (FPGA-based) FFT implementations, we see that the degree of configurability is less than what is desired. In this paper, a new FFT architecture is proposed, which has a high degree of run-time configurability and yet does not compromise area or throughput. The configurable parameters of this design are the number of FFT points (up to 64K), forward versus inverse mode, output order (natural or bit-reversed), and the number of streams (up to 4). The proposed FFT architecture (HC-FFT) is designed using a parallel and pipelined radix-2 multipath delay commutator (MDC) FFT structure. HC-FFT was implemented on a Xilinx Kintex Ultrascale FPGA and was verified against the Xilinx FFT IP. Besides its high degree of run-time configurability, HC-FFT is quite efficient and offers a very high throughput of 87 Gbps with a quite reasonable area.

A Flexible-Channel MDF Architecture for Pipelined Radix-2 FFT

“…According to the different number of channels in the structure, pipelined structures can be divided into two categories: S (Single-path) and M (Multi-path), which can be combined with DF and DC to form a variety of structures such as SDF, MDC [7] and SDC [8]. At present, there are also many parallel structures proposed based on these pipelined structures [9]- [10]. The basic algorithms used to implement pipelined FFT have different cardinalities [11]- [16].…”