HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System

Li, Renwei; Wu, Junning; Liu, Meng; Chen, Zuding; Zhou, Shenggang; Feng, Shanggong

doi:10.23919/date48585.2020.9116551

Cited by 6 publications

(4 citation statements)

References 8 publications

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“…An rBRIEF-based feature extraction approach is then presented by [121] to further improve the feature matching quality. To help optimize the tracking task in the vSLAM system with high-performance and energy-efficient, Li et al [122] design a specialized CMOS-based hardware accelerator to help perform high-quality feature extraction and high-precision descriptor generation. The design is compatible with ORB-SLAM system requirements and can be integrated into any SoC architecture.…”

Section: Sparse Slam On Fpgamentioning

confidence: 99%

A Survey of FPGA-Based Robotic Computing

Wan

Bo²,

Li³

et al. 2020

Preprint

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Recent researches on robotics have shown significant improvement, spanning from algorithms, mechanics to hardware architectures. Robotics, including manipulators, legged robots, drones, and autonomous vehicles, are now widely applied in diverse scenarios. However, the high computation and data complexity of robotic algorithms pose great challenges to its applications. On the one hand, CPU platform is flexible to handle multiple robotic tasks. GPU platform has higher computational capacities and easy-touse development frameworks, so they have been widely adopted in several applications. On the other hand, FPGA-based robotic accelerators are becoming increasingly competitive alternatives, especially in latency-critical and power-limited scenarios. With specialized designed hardware logic and algorithm kernels, FPGA-based accelerators can surpass CPU and GPU in performance and energy efficiency. In this paper, we give an overview of previous work on FPGA-based robotic accelerators covering different stages of the robotic system pipeline. An analysis of software and hardware optimization techniques and main technical issues is presented, along with some commercial and space applications, to serve as a guide for future work.

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Section: Sparse Slam On Fpgamentioning

confidence: 99%

A Survey of FPGA-Based Robotic Computing

Wan

Bo²,

Li³

et al. 2020

Preprint

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“…This achieved a frame rate of 33.2 frames per second. The first CMOS-based dedicated hardware accelerator was proposed (HcveAcc) byLi Renwei et al (2020), which was implemented in 28 nm CMOS technology using commercial EDA tools [17]. HcveAcc solved the time-cost bottleneck in the tracking process-high-density feature extraction and high-precision descriptor generation.…”

Section: Introductionmentioning

confidence: 99%

“…According to Equations(17) and(18), A and b are calculated through six sets of filters. For each point, perform six sets of 11 × 11 2D filtering, with 22 multiply − accumulate(MAC ), 7 multiplications, and 2 additions, resulting in a computational cost of22MAC + 7 × Mult + 2 × Add (32)where MAC is equivalent to 11 multiplications and 19 additions.…”

mentioning

confidence: 99%

FPGA-Based Feature Extraction and Tracking Accelerator for Real-Time Visual SLAM

Zhang,

Xiong,

Liu

et al. 2023

Sensors

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Due to its advantages of low latency, low power consumption, and high flexibility, FPGA-based acceleration technology has been more and more widely studied and applied in the field of computer vision in recent years. An FPGA-based feature extraction and tracking accelerator for real-time visual odometry (VO) and visual simultaneous localization and mapping (V-SLAM) is proposed, which can realize the complete acceleration processing capability of the image front-end. For the first time, we implement a hardware solution that combines features from accelerated segment test (FAST) feature points with Gunnar Farneback (GF) dense optical flow to achieve better feature tracking performance and provide more flexible technical route selection. In order to solve the scale invariance and rotation invariance lacking problems of FAST features, an efficient pyramid module with a five-layer thumbnail structure was designed and implemented. The accelerator was implemented on a modern Xilinx Zynq FPGA. The evaluation results showed that the accelerator could achieve stable tracking of features of violently shaking images and were consistent with the results from MATLAB code running on PCs. Compared to PC CPUs, which require seconds of processing time, the processing latency was greatly reduced to the order of milliseconds, making GF dense optical flow an efficient and practical technical solution on the edge side.

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“…Field Programmable Gate Arrays (FPGAs), known for their reconfigurable nature, offer flexible configuration and cost-effective engineering experimentation. They stand as an ideal development platform for hardware acceleration applications and prototype validation [4,5]. The numerous advantages mentioned above have led to their widespread adoption.…”

Section: Introductionmentioning

confidence: 99%

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Liu,

Wang,

2023

Electronics

Self Cite

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Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption.

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HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System

Cited by 6 publications

References 8 publications

A Survey of FPGA-Based Robotic Computing

A Survey of FPGA-Based Robotic Computing

FPGA-Based Feature Extraction and Tracking Accelerator for Real-Time Visual SLAM

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

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