HDTrans

Abstract

Dynamic translation is a general purpose tool used for instrumenting programs at run time. Many current translators perform substantial rewriting during translation in an attempt to reduce execution time. When dynamic translation is used as a ubiquitous policy enforcement mechanism, the majority of program executions have no dominating inner loop that can be used to amortize the cost of translation. Even under more favorable usage assumptions, our measurements show that such optimizations offer no significant benefit in most cases. A simpler, more maintainable, adaptable, and smaller translator may be preferable to more complicated designs. In this paper, we present HDTrans, a light-weight IA-32 to IA-32 binary translation system that uses some simple and effective translation techniques in combination with established trace linearization and code caching optimizations. We also present an evaluation of translation overhead under non-ideal conditions, showing that conventional benchmarks do not provide a good prediction of translation overhead when used pervasively. A further contribution of this paper is an analysis of the effectiveness of post-compile static pre-translation techniques for overhead reduction. Our results indicate that static pre-translation is effective only when expensive instrumentation or optimization is performed, and that efficient reload of pre-translated code incurs a substantial execution-time penalty.

Low overhead dynamic binary translation on ARM

“…DynamoRIO [8], Pin [19], Valgrind [20], HDTrans [23] and fastBT [21] are DBTs designed for program instrumentation which have the same host and source architectures. The last two do not perform register state recovery when translating signals, and thus may cause some applications to malfunction.…”

Performance simulation methodologies for hardware/software co-designed processors

“…Although there is a large number of publications that quantify the overhead in DBT architectures [20,50,22,10,26] the authors do not classify the source of this overhead. Other studies focus on one specific overhead: interpretation overhead [50,68], branch resolution [70], indirect branches overhead [32] etc. Our results are more detailed as they are not limited to the global overhead but show the breakdown.…”

Indirect branch emulation techniques in virtual machines

“…Sridhar et al [35,36] describe HDTrans, a dynamic binary translator that is performanceefficient, although it does not employ any code optimization technique. One of the reasons for its efficiency is the introduction of two novel indirect branch emulation techniques: the Sieve, for register-indirect jumps, and the Return Cache for return instructions (see Section 4.6 and Section 4.9).…”