Height Uniformity Simulation and Experimental Study of Electroplating Gold Bump for 2.5D/3D Integrated Packaging

Abstract

With the rapid development of nano/micro technology for commercial electronics, the typical interconnection method could not satisfy the high power-density packaging requirement. The 2.5D/3D integrated packaging was seen as a promising technology for nano/micro systems. The gold (Au) bump was the frequently used bonding method for these systems because of its excellent thermal, electric, and mechanical performance. However, relatively little work has been performed to analyze its height uniformity. In this study, the simulation and experimental methods were used to analyze the Au bump height uniformity. Firstly, the electroplating process of Au bump under different flow field parameters was simulated by COMSOL software. The simulated results indicated that the Au+ concentration polarization was the significant reason that caused the non-uniform distribution of Au bump along the wafer radius. Meanwhile, the flow field parameters, such as inlet diameter, inlet flow, titanium (Ti), wire mesh height, and Ti wire mesh density, were optimized, and their values were 20 mm, 20 L/min, 12 mm, and 50%, respectively. Subsequently, the Au bump height uniformity under different current densities was analyzed through an experimental method based on these flow field parameters. The experimental results showed that the increases of current density would decrease the Au bump height uniformity. When the current density was 0.2 A/dm2, the average height, range, and deviance values of Au bump were 9.04 μm, 1.33 μm, and 0.43 μm, respectively, which could reach the requirement of high density and precision for 2.5D/3D integrated packaging.

Research of Vertical via Based on Silicon, Ceramic and Glass

“…(1) Electroplating is carried out in a segmented current mode, and the electroplating effect can be ensured by adding jitter settings; (2) The bottom-up electro-plating process has improved the problem of the large stress caused by excessive edge thickness due to an uneven rate; (3) The problem of slit defects or bulge/void defects can be solved by two-step electroplating.…”

“…Three-dimensional (3D) integration has the advantages of low power consumption, small form factor, high performance and high functional density [ 1 , 2 , 3 , 4 ]. It can meet the interconnection requirements of low latency and low power consumption by shortening the interconnection length [ 5 , 6 , 7 , 8 ].…”