HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs

Campanoni, Simone; Brownell, Kevin; Kanev, Svilen; Jones, Timothy M.; Wei, Gu-Yeon; Brooks, David

doi:10.1109/isca.2014.6853215

Cited by 21 publications

(38 citation statements)

References 44 publications

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“…Campanoni et al [2012] extract parallelism by running iterations of a loop on separate threads, fulfilling loop-carried dependences using signals between threads. They also propose an architectural improvement to make their approach more feasible [Campanoni et al 2014]. Our approach tries to detect parallel patterns in sequential code and suggests a solution without any special architectural requirements other than those commonly satisfied.…”

Section: Related Workmentioning

confidence: 99%

Using Template Matching to Infer Parallel Design Patterns

Huda

Jannesari

Wolf

2015

ACM Trans. Archit. Code Optim.

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The triumphant spread of multicore processors over the past decade increases the pressure on software developers to exploit the growing amount of parallelism available in the hardware. However, writing parallel programs is generally challenging. For sequential programs, the formulation of design patterns marked a turning point in software development, boosting programmer productivity and leading to more reusable and maintainable code. While the literature is now also reporting a rising number of parallel design patterns, programmers confronted with the task of parallelizing an existing sequential program still struggle with the question of which parallel pattern to apply where in their code. In this article, we show how template matching, a technique traditionally used in the discovery of sequential design patterns, can also be used to support parallelization decisions. After looking for matches in a previously extracted dynamic dependence graph, we classify code blocks of the input program according to the structure of the parallel patterns we find. Based on this information, the programmer can easily implement the detected pattern and create a parallel version of his or her program. We tested our approach with six programs, in which we successfully detected pipeline and do-all patterns.

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Section: Related Workmentioning

confidence: 99%

Using Template Matching to Infer Parallel Design Patterns

Huda

Jannesari

Wolf

2015

ACM Trans. Archit. Code Optim.

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“…We used the second version of the HELIX compiler, HCCv2 [5], which is based on the ILDJIT compilation framework [2]. The sequential programs used as baseline were the unmodified versions of benchmarks, optimized (O3) and compiled by ILDJIT with LLVM 3.4.1 as the back end.…”

Section: Methodsmentioning

confidence: 99%

“…Contrary to common assumptions, there is considerable latent TLP even in non-numerical sequentially designed programs, e.g., between the iterations of a loop [5,3,4,20]. When such iterations can run unfettered on multiple cores in a modern processor, performance adjusts with the number of cores.…”

Section: Helix-upmentioning

confidence: 99%

Power-awareness and smart-resource management in embedded computing systems

Santambrogio¹,

Ayala²,

Campanoni³

et al. 2015

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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Resources such as quantities of transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer science abstractions have not changed since the 1960's. Therefore this is the time for a fresh approach to the way systems are designed and used.

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“…HELIX-RC [3] proposes a ring-cache architecture to communicate register dependences. XLOOPS is potentially more elegant as it avoids requiring ISA extensions to specify the dependence communication unlike previous proposals.…”

Section: Related Workmentioning

confidence: 99%

“…Previous speculative parallelization techniques show promise but demand dramatic changes in the microarchitecture, compiler, and/or ISA. HELIX-RC [3] takes an alternative approach of decoupling memory dependence communication without employing speculation but relies on an aggressive parallelizing compiler. The XLOOPS ISA could be extended to include instructions for lane synchronization to benefit compiler optimizations as in HELIX-RC.…”

Section: Related Workmentioning

confidence: 99%

Architectural Specialization for Inter-Iteration Loop Dependence Patterns

Srinath

Ilbeyi

Tan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Hardware specialization is an increasingly common technique to enable improved performance and energy efficiency in spite of the diminished benefits of technology scaling. This paper proposes a new approach called explicit loop specialization (XLOOPS) based on the idea of elegantly encoding inter-iteration loop dependence patterns in the instruction set. XLOOPS supports a variety of inter-iteration dataand control-dependence patterns for both single and nested loops. The XLOOPS hardware/software abstraction requires only lightweight changes to a general-purpose compiler to generate XLOOPS binaries and enables executing these binaries on:(1) traditional microarchitectures with minimal performance impact, (2) specialized microarchitectures to improve performance and/or energy efficiency, and (3) adaptive microarchitectures that can seamlessly migrate loops between traditional and specialized execution to dynamically trade-off performance vs. energy efficiency. We evaluate XLOOPS using a vertically integrated research methodology and show compelling performance and energy efficiency improvements compared to both simple and complex general-purpose processors.

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HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs

Cited by 21 publications

References 44 publications

Using Template Matching to Infer Parallel Design Patterns

Using Template Matching to Infer Parallel Design Patterns

Power-awareness and smart-resource management in embedded computing systems

Architectural Specialization for Inter-Iteration Loop Dependence Patterns

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