HEPS-BPIX, a hybrid pixel detector system for the High Energy Photon Source in China

Zhang, J.; Wei, W.; Gu, Jiahui; Shen, Wei; Li, Z.; Ning, Z.; Fan, Lei; Chen, M.; Lu, Y.; Ma, Xiaoyan; Jiang, X. S.; Lan, Aiping; Ouyang, Q.; Liu, P.; Wang, Zheng

doi:10.1088/1748-0221/12/01/c01041

Cited by 13 publications

(4 citation statements)

References 6 publications

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“…The HEPS-BPIX is expected to be utilized at most of the beamlines in HEPS, particularly for large molecule crystallography, Laue diffraction, and other synchrotron radiation applications that demand noise-free pixels and high pixel resolution. Up to now, the HEPS-BPIX detector has been undergoing iterative upgrades and transitions from single-threshold to dual-threshold functionality [1][2][3][4][5]. The system is required to handle a multitude of diverse types of information, and users have the capability to remotely connect to the detectors via independent software or a distributed control system.…”

Section: Heps-bpix Systemmentioning

confidence: 99%

A study of the latest updates of the readout system for the hybird-pixel detector at HEPS

Li,

Zhang,

Wei

et al. 2024

J. Inst.

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The High Energy Photon Source (HEPS) represents a fourth-generation light source. This facility has made unprecedented advancements in accelerator technology, necessitating the development of new detectors to satisfy physical requirements such as single-photon resolution, large dynamic range, and high frame rates. Since 2016, the Institute of High Energy Physics has introduced the first user-experimental hybrid pixel detector, progressing to the fourth-generation million-pixel detector designed for challenging conditions, with the dual-threshold single-photon detector HEPS-Beijing PIXel (HEPS-BPIX) set as the next-generation target. HEPS-BPIX will employ the entirely new Application-Specific Integrated Circuit (ASIC) BP40 for pixel information readout. Data flow will be managed and controlled through readout electronics based on a two-tier Field-Programmable Gate Array (FPGA) system: the Front-End Electronics (FEE) and the Input-Output Board (IOB) handle the fan-out for 12 ASICs, and the μ4FCP is tasked with processing serial data on high-speed links, transferring pixel-level data to the back-end RTM and μTCA chassis, or independently outputting through a network port, enabling remote control of the entire detector. The new HEPS-BPIX firmware has undergone a comprehensive redesign and update to meet the electronic characteristics of the new chip and to improve the overall performance of the detector. We provide an overview of the core subunits of HEPS-BPIX, emphasizing the readout system, evaluating the new hardware and firmware, and highlighting some of its innovative features and characteristics.

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Section: Heps-bpix Systemmentioning

confidence: 99%

A study of the latest updates of the readout system for the hybird-pixel detector at HEPS

Li,

Zhang,

Wei

et al. 2024

J. Inst.

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“…The flexibility of the uFC with its variety of interfaces enables it to be used in various configurations. We adopted it as part of the second generation hybrid pixel detector (HEPS-BPIX) [12] for the HEPS in China. This prototype system was assembled with sixteen front-end modules including 1M pixels in total, covering an area of 16.32 cm x 18.3 cm ( Figure 5).…”

Section: Example Use In Hepsmentioning

confidence: 99%

The MicroTCA Fast Control Board for Generic Control and Data Acquisition Applications in HEP Experiments

Zhang

Jiang

2019

IEEE Trans. Nucl. Sci.

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To provide the generic clock, trigger and control function and fulfill the data transmission performance requirement in high energy physics (HEP) experiments, a MicroTCA Fast Control board (uFC) was developed based on the Advanced Mezzanine Card (AMC) specification. Built around the Xilinx Kintex-7 FPGA, the uFC provides users with a platform with data memory, reference clock, trigger and SFP+ (Small Form-factor Pluggable) connections that are required in general experiment. In addition, it has access to two on-board FPGA Mezzanine Card (FMC) sockets with a large array of configurable I/O and high-speed links up to 10 Gbps. This paper presents test results from the first set of pre-production prototypes and reports on the application in High Energy Photon Source in China.

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“…At the same time, the hardware uses DDR3 as data cache and then processes and transfers packets through the high-speed GTX transceiver [4]. For single-module readout system, PHY layer connects directly to the SFP plus interface and through the optical fiber to the upper computer [6].…”

Section: Hardware and Firmware Implementationmentioning

confidence: 99%

A readout method based on 10 Gigabit Ethernet for Sipixel detector

Li,

Zhang,

et al. 2018

Preprint

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With the rapid development of network protocol, TCP/IP has been widely applied in various OS systems because of its advantages of high-speed network transmission and standardization. Furthermore, TCP/IP has the functions of retransmission and flow control, so it can ensure data's security and stability. In recent years, as a transmission Field-bus, it is also widely used in high-energy physics detectors. This article describes a readout method using 10 gigabit network processor applied in silicon pixel detector which is a pixel detector designed for the High Energy Photon Source (HEPS) in China. The PHY layer and the MAC layer of this hardware are both instantiated in FPGA. The logic of hardware can process and read out the data of the detectors. Meanwhile, it wraps up data and send them to TOE (TCP Offload Engine). A kind of bus control protocol interface is also provided, which can facilitate the host computer to read and write the specific register directly through the UDP protocol. Only a piece of FPGA can complete the processing of the TCP and UDP packets. It is important for the miniaturization of the detectors.

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HEPS-BPIX, a hybrid pixel detector system for the High Energy Photon Source in China

Cited by 13 publications

References 6 publications

A study of the latest updates of the readout system for the hybird-pixel detector at HEPS

A study of the latest updates of the readout system for the hybird-pixel detector at HEPS

The MicroTCA Fast Control Board for Generic Control and Data Acquisition Applications in HEP Experiments

A readout method based on 10 Gigabit Ethernet for Sipixel detector

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