Hetero structure PNPN tunnel FET: Analysis of scaling effects on counter doping

Joseph, H. Bijo; Singh, Sankalp Kumar; Hariharan, R.; Priya, P. Aruna; Kumar, Naveen; Thiruvadigal, D. John

doi:10.1016/j.apsusc.2018.01.274

Cited by 12 publications

(7 citation statements)

References 23 publications

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“…The increase in tunneling distance offers more tunneling resistance for the carriers. 20 This tunneling resistance may originate owing to the intensity of fringing field from gate oxide to source (shell) end. This could firmly affect the tunneling current conduction mechanism for core-shell TFET owing to the fact that the gate and source were reverse biased.…”

Section: Resultsmentioning

confidence: 99%

Impact of Fringing Field on Shell Radius and Spacer Dielectric on Device Performance of InAs-GaSb Core-Shell Nanowire nTFET

Joseph

Singh

Nagarajan

et al. 2021

ECS J. Solid State Sci. Technol.

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A comprehensive investigation with the help of 3D device simulation, we demonstrate the impact of fringing field on shell radius of InAs-GaSb core–shell nanowire n-channel tunnel field effect transistor (TFET) in this paper. Increase in shell radius intensifies the magnitude of fringing electric field towards shell region. This results in generation of depletion zone in the shell near the gate edge affects the device performance metrics such as on current and threshold voltage. It is demonstrated that by appropriate gate engineering the influence of fringing electric field can be circumvent. High-k spacer dielectric at the gate underlap shows improvement in device performance metrics such as on current with sub 2.3 k B T q subthreshold swing. An investigation of the effect of drain voltage on the device characteristics exhibits the privation of tunneling resistance limited region. Furthermore, the output characteristics for such an architecture bear a resemblance to long channel MOSFET (metal oxide semiconductor field effect transistor).

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Section: Resultsmentioning

confidence: 99%

Impact of Fringing Field on Shell Radius and Spacer Dielectric on Device Performance of InAs-GaSb Core-Shell Nanowire nTFET

Joseph

Singh

Nagarajan

et al. 2021

ECS J. Solid State Sci. Technol.

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“…A dual k spacer with a high k (HfO 2 ) inner layer and low k (SiO 2 ) outer layer can improve the TFET performance by improving the coupling of the fringing field to the source channel junction 33 . The proposed TFET structure amalgams some ideas, which gives enhanced performance compared to the others 9,10,13,and . The dimension of the proposed TFET is optimized and mentioned in Table 1.…”

Section: Device Dimensionmentioning

confidence: 99%

“…TFET is useful for ultralow power applications with SS below 60 mV/decade. Different structures of TFET have been developed to achieve a high switching ratio and low SS [6][7][8][9][10][11][12][13] ; however, a major hurdle is the low on-state current. 14 The scaling of device parameters has a considerable impact on the DC as well as analog/radio frequency (RF) characteristics of TFET as well.…”

Section: Introductionmentioning

confidence: 99%

Technology computer‐aided design simulation of G e‐source double‐gate S i‐tunnel Field Effect Transistor: Radio frequency and linearity analysis

Baruah

Debnath

Baishya

2022

Int J RF Mic Comp-Aid Eng

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This article presented a thorough investigation of direct current (DC), analog/ radio frequency (RF), and linearity performance of a proposed Ge-source double gate planner Si-tunnel field-effect transistor (TFET) considering different parameter variations using Sentaurus TCAD 2-D device simulator. The analyses are performed using various quality matrices such as transconductance (g m ), total gate capacitance (C gg ), unity gain cut-off frequency (f T ), gainbandwidth product (GBP), transconductance frequency product (TFP), etc. It can be perceived that the inclusion of source/channel junction pocket, low bandgap source material, high k gate dielectric, and dual k spacer technology can improve the TFET performances in terms of on-current (I ON ), off-current (I OFF ), on-off current ratio (I ON / I OFF ) and subthreshold swing (SS) at a supply voltage V DS = 0.7 V. In this article, we used a non-quasi-static (NQS) smallsignal model to analyze the behavior of the proposed device in high-frequency regions. Based on this, the small-signal admittance parameters were validated up to 1 THz. The proposed TFET produced RF figures of merit (FoM), cut-off frequency (f T ), and maximum oscillation frequency (f max ) in the terahertz range at V DS = V GS = 1 V. Linearity and distortion parameters considered here are VIP2 (interpolated input voltage at which first and second harmonics are equal), VIP3 (interpolated input voltage at which first and third harmonics are similar), IIP3 (third-order input intercept point), IMD3 (third-order intermodulation distortion), 1-dB compression point, HD2 (second-order harmonic), HD3 (third-order harmonic) and THD (total harmonic distortion) for different supply voltages. According to the study, the proposed TFET can provide improved RF and linearity performance, ensuring device reliability in lowpower, high-frequency applications. K E Y W O R D Sband to band tunneling (BTBT), cut-off frequency (f T ), gain-bandwidth product (GBP), linearity, transconductance frequency product (TFP), tunnel field-effect transistor (TFET)

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“…Among these, it has been reported that the method of forming a p-n-p-n structure by inserting a counter-doped pocket next to the source can improve the oncurrent and SS by increasing the lateral electric field [21]- [24]. Simulation studies of TFETs with counter-doped pockets have been conducted in a structure with a pocket and source attached [21], [25]- [27]. However, when an n-type pocket is formed next to a p-type source by tilt implantation or epitaxial growth, a region with reduced doping concentration is inevitably created because of counter-doping at the sourcepocket junction [28].…”

Section: Introductionmentioning

confidence: 99%

Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs

2023

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The effects of low net-doped region on the electrical performance of tunnel field-effect transistors (TFETs) are investigated using TCAD simulation. Compared with previous studies, it is observed that the low net-doped region between the source and pocket can enhance TFET electrical characteristics such as on-current (Ion) and subthreshold swing (SS) with fine on-off current ratio (Ion/Ioff). By optimizing the length of the low net-doped region, Ion increased 14.6 times and the SS is reduced by 34.6 % compared with the TFET where the low net-doped region was not considered. Furthermore, guidelines for designing counterdoped pocket are proposed considering the low net-doped region. The local minimum in the conduction band can be used to further improve the on-current and SS performance by adjusting the pocket width and doping concentration. To avoid pocket-induced SS degradation, the pocket doping concentration must also be taken into account when determining the optimal value of the pocket width and vice versa.INDEX TERMS Tunnel field-effect transistor (TFET), counter-doped pocket, low net-doped region, pocket width, tunneling width

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Hetero structure PNPN tunnel FET: Analysis of scaling effects on counter doping

Cited by 12 publications

References 23 publications

Impact of Fringing Field on Shell Radius and Spacer Dielectric on Device Performance of InAs-GaSb Core-Shell Nanowire nTFET

Impact of Fringing Field on Shell Radius and Spacer Dielectric on Device Performance of InAs-GaSb Core-Shell Nanowire nTFET

Technology computer‐aided design simulation of G e‐source double‐gate S i‐tunnel Field Effect Transistor: Radio frequency and linearity analysis

Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs

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