Heterodyne Phase Locking: A Technique for High-Frequency Division

Abstract

The task of frequency division entails serious challenges at speeds greater than a few tens of gigahertz as flip-flop-based topologies fail and narrowband alternatives emerge as the only viable solution. These alternatives include the Miller regenerative topology and injection-locked oscillators, both of which suffer from a narrow lock range at very high frequencies. For example, the injection-locked divider in [1] achieves a lock range of about 1.5% if no external tuning is applied. Furthermore, these topologies do not readily lend themselves to divide ratios greater than 2 [2]. This paper introduces the concept of "heterodyne phase locking," a technique that can be used to construct high-speed dividers with arbitrary integer or fractional divide ratios. Consider the phase-locked loop (PLL) shown in Fig. 23.6.1, where the phase detector (e.g., a single mixer) is replaced with a cascade of N mixers that are driven by the voltage-controlled oscillator (VCO) output. It is assumed that each mixer is followed by a filter to remove the sum frequency generated by that mixer. In a manner similar to a heterodyne receiver, this cascade of mixers downconverts the input N times, producing a dc component at node X if f in =N•f out . In other words, if the loop locks, then f out =f in /N.Heterodyne phase locking offers a number of advantages over other frequency division techniques. First, a divide ratio of, say, 3 is as easily afforded as a divide ratio of 2 -a sharp contrast to flip-flop-based and injection-locked topologies. In fact, as N increases, the only trade-offs that arise are from the necessary reduction of the loop bandwidth, which is tolerable so long as the settling of the PLL is much faster than that of the synthesizer in which it is embedded, and the higher loading imposed on the oscillator, which can be accommodated because the oscillator operates at a proportionally lower frequency.The second advantage is associated with the lock range. Using a relatively high loop gain (while maintaining a reasonable phase margin), the PLL can achieve a lock range almost equal to the tuning range of the oscillator, which is typically 5 to 10 times the lock range of an injection-locked divider. Note that external (discrete or continuous) tuning techniques applied to injection-locked dividers [1, 2] can be used here as well to further widen the lock range.The third advantage relates to the output phase noise. Injectionlocked dividers, if designed for higher speeds, require that, on the one hand, the tank Q be scaled up to maintain a constant phase noise and, on the other hand, the tank Q be constant to maintain a constant fractional lock range. Therefore, these dividers suffer from a trade-off between the tank Q and produce greater phase noise as the circuit approaches the edge of the lock range. Heterodyne PLLs, however, entail no such trade-offs if their loop gain remains high.Heterodyne phase-locking can also provide fractional divide ratios. If a ÷M circuit is inserted in the feedback path of Fig. 23.6.1, then f out =M•...

Analysis of Injection-Locked Regenerative Frequency Dividers

“…The block diagram of a frequency divider based on the heterodyne phase locking technique [10] is shown in Fig. 4.1b.…”

CMOS Transceivers at 60 GHz and Beyond1

“…This section presents the concept of "heterodyne phaselocking," a technique that can be used to construct high-speed dividers with arbitrary integer or fractional divide ratios [8]. Consider the phase-locked loop (PLL) shown in Fig.…”

Stability and Operation of Injection-Locked Regenerative Frequency Dividers

“…The block diagram of a frequency divider based on the heterodyne phase-locking technique [10] is shown in Fig. 1(b).…”

“…Moreover, it can neither provide quadrature output phases nor achieve a 50% duty cycle. [10], and (c) generalized injection-locked regenerative frequency divider.…”