HeteroFlow

Abstract

To achieve high performance with FPGA-equipped heterogeneous compute systems, it is crucial to co-optimize data placement and compute scheduling to maximize data reuse and bandwidth utilization for both on-and off-chip memory accesses. However, optimizing the data placement for FPGA accelerators is a complex task. One must acquire in-depth knowledge of the target FPGA device and its associated memory system in order to apply a set of advanced optimizations. Even with the latest high-level synthesis (HLS) tools, programmers often have to insert many low-level vendor-specific pragmas and substantially restructure the algorithmic code so that the right data are accessed at the right loop level using the right communication schemes. These code changes can significantly compromise the composability and portability of the original program.To address these challenges, we propose HeteroFlow, an FPGA accelerator programming model that decouples the algorithm specification from optimizations related to orchestrating the placement of data across a customized memory hierarchy. Specifically, we introduce a new primitive named .to(), which provides a unified programming interface for specifying data placement optimizations at different levels of granularity: (1) coarse-grained data placement between host and accelerator, (2) medium-grained kernel-level data placement within an accelerator, and (3) fine-grained data placement within a kernel. We build HeteroFlow on top of the open-source HeteroCL DSL and compilation framework. Experimental results on a set of realistic benchmarks show that, programs written in HeteroFlow can match the performance of extensively optimized manual HLS design with much fewer lines of code. CCS CONCEPTS• Hardware → Hardware description languages and compilation; High-level and register-transfer level synthesis;

Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow

“…Those kernels are functional but not optimized (e.g. buffer sizing, burst transfer), and could be improved as future work on heterogeneous optimization [35,40].…”

“…On the contrary, PREESM considers kernels as black boxes without assumptions on their inner C++ code. HeteroFlow [40] too takes Halide as an input, via the HeteroHalide [27] compiler. While HeteroFlow supports data transfer directives written by the designer, as well as buffer reuse, it does not embed a delay type system to perform buffer sizing.…”

Exploring Sparse Visual Odometry Acceleration With High-Level Synthesis

“…Since (10) is nonlinear in T k,k−1 , it needs to be solved using an iterative Gauss-Newton method. Given an estimation of the relative transformation Tk,k−1 , an incremental update T (ξ) of the estimate can be parameterized with a twist coordinate ξ ∈ se(3).…”

“…The IRC and FA hardware accelerators as well as the host code are developed using Xilinx SDSoC 2019.1 and HLS C/C++. We also utilize the state-of-the-art HeteroFlow [10] to develop IRC and FA designs. With HeteroFlow, we generate only the HLS C/C++ code for the accelerators, as it does not support SDSoC nor the Xilinx ZU9EG FPGA.…”

“…We first perform an end-to-end profiling analysis to identify the bottleneck of SVO. After that, we develop the FPGA accelerator to reduce the computational overhead by using state-of-the-art software-hardware co-design tools and HLS tools such as Xilinx Software-Defined System-on-Chip (SD-SoC) and HeteroFlow [10]. Then, we apply the proposed methods to the FPGA accelerator to reduce the data transfer overhead between CPU and FPGA accelerators.…”