Heterogeneous 2.5D integration on through silicon interposer

Zhang, Xiaowu; Lin, Jong Kai; Wickramanayaka, Sunil; Zhang, Songbai; Weerasekera, Roshan; Dutta, Rahul; Chang, K. W.; Chui, King-Jien; Li, Hong Yu; Ho, David; Liu, Ding; Katti, Guruprasad; Bhattacharya, Shuvajit; Kwong, D. L.

doi:10.1063/1.4921463

Cited by 129 publications

(38 citation statements)

References 122 publications

(172 reference statements)

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“…The method of fabricating pillars or nanowires by MacEtch using interconnected mesh patterned catalyst layers has been well demonstrated, reaching aspect ratios as high as 200 for uniform nanowire arrays . The process of fabricating high aspect ratio vias using MacEtch, which requires discrete dot catalyst patterns, is an important technique that can be applied to high density 2.5D/3D memory, interconnects, through silicon vias (TSVs), photonic crystals, detectors, and many other technologies. Replacing the conventional reactive ion etching (RIE) process with MacEtch can minimize the unrepairable surface damages, including scallops and defects that can significantly degrade device performance .…”

Section: Introductionmentioning

confidence: 99%

Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport

Kim

Mohseni

Balasundaram

et al. 2017

Adv Funct Materials

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Metal-assisted chemical etching (MacEtch) has shown tremendous success as an anisotropic wet etching method to produce ultrahigh aspect ratio semiconductor nanowire arrays, where a metal mesh pattern serves as the catalyst. However, producing vertical via arrays using MacEtch, which requires a pattern of discrete metal disks as the catalyst, has often been challenging because of the detouring of individual catalyst disks off the vertical path while descending, especially at submicron scales. Here, the realization of ordered, vertical, and high aspect ratio silicon via arrays by MacEtch is reported, with diameters scaled from 900 all the way down to sub-100 nm. Systematic variation of the diameter and pitch of the metal catalyst pattern and the etching solution composition allows the extraction of a physical model that, for the first time, clearly reveals the roles of the two fundamental kinetic mechanisms in MacEtch, carrier generation and mass transport. Ordered submicron diameter silicon via arrays with record aspect ratio are produced, which can directly impact the through-silicon-via technology, high density storage, photonic crystal membrane, and other related applications.

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Section: Introductionmentioning

confidence: 99%

Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport

Kim

Mohseni

Balasundaram

et al. 2017

Adv Funct Materials

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“…Different layers can communicate using NW through-silicon vias (TSVs). Similar low-power/highperformance advantages can be realized through achievement of high interconnect densities on the 2.5D though-Siinterposer (TSI) as reported in [114].…”

Section: Discussionmentioning

confidence: 91%

Nanowire Optoelectronics

Wang

Nabet

2015

Nanophotonics

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Semiconductor nanowires have been used in a variety of passive and active optoelectronic devices including waveguides, photodetectors, solar cells, light-emitting diodes (LEDs), lasers, sensors, and optical antennas. We review the optical properties of these nanowires in terms of absorption, guiding, and radiation of light, which may be termed light management. Analysis of the interaction of light with long cylindrical/hexagonal structures with subwavelength diameters identifies radial resonant modes, such as Leaky Mode Resonances, or Whispering Gallery modes. The two-dimensional treatment should incorporate axial variations in "volumetric modes," which have so far been presented in terms of Fabry-Perot (FP), and helical resonance modes. We report on finite-difference timedomain (FDTD) simulations with the aim of identifying the dependence of these modes on geometry (length, width), tapering, shape (cylindrical, hexagonal), core-shell versus core-only, and dielectric cores with semiconductor shells. This demonstrates how nanowires (NWs) form excellent optical cavities without the need for top and bottom mirrors. However, optically equivalent structures such as hexagonal and cylindrical wires can have very different optoelectronic properties meaning that light management alone does not sufficiently describe the observed enhancement in upward (absorption) and downward transitions (emission) of light in NWs; rather, the electronic transition rates should be considered. We discuss this "rate management" scheme showing its strong dimensional dependence, making a case for photonic integrated circuits (PICs) that can take advantage of the confluence of the desirable optical and electronic properties of these nanostructures.

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“…Contrary to 3D stacking, heterogeneous 2.5D integration takes a co-planar approach and interconnects chips either through a common platform [4]. Depending on the level of integration, this common platform may be silicon interposer ( Fig.…”

Section: A Multi-chip Integrationmentioning

confidence: 99%

“…The new integration trends have strong consequences on the design of the communications backbone within the package. On the one hand, with the recent introduction of silicon interposers in 2.5D processes, there has been a reduction of the performance and cost difference between on-chip and offchip communication [4]. Also, interposers may be capable of hosting off-chip routers in the future [2].…”

Section: Introductionmentioning

confidence: 99%

Channel Characterization for Chip-scale Wireless Communications within Computing Packages

Timoneda

Cabellos‐Aparicio

Manessis

et al. 2018

2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)

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Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.

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Heterogeneous 2.5D integration on through silicon interposer

Cited by 129 publications

References 122 publications

Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport

Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport

Nanowire Optoelectronics

Channel Characterization for Chip-scale Wireless Communications within Computing Packages

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