Heterogeneous 3-D circuits: Integrating free-space optics with CMOS

Savidis, Ioannis; Çiftçioğlu, Berkehan; Xu, Jie; Hu, Jianyun; Jain, Manish; Berman, Rebecca; Xue, Jing; Liu, Peng; Moore, Duncan T.; Wicks, G. W.; Huang, Michael C.; Friedman, Eby G.

doi:10.1016/j.mejo.2015.10.004

Cited by 8 publications

(3 citation statements)

References 33 publications

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“…-125 could offer significant advantages over free-space optical interconnects [42] due to the small coupler size, the short in-plane optical path lengths, compatibility with CMOS fabrication and the elimination of vertical alignment and packaging issues. Moreover, the ultra-compact and ultra-broadband operation of 2P-NA HVC are attractive for ultra-broadband biophotonic applications such as two-photon fluorescence spectroscopy and surface-enhanced coherent-anti-Stokes Raman spectroscopy [43,44].…”

Section: Introductionmentioning

confidence: 99%

“…Unlike conventional ECs and VCs, this coupler has a comparable size to CMOS devices in VLSI circuits [39–41] (in contrast to ECs and VCs), making it a good candidate for cross‐chip and board‐to‐board optical communication links (photonic‐electronic convergence). Such links could offer significant advantages over free‐space optical interconnects [42] due to the small coupler size, the short in‐plane optical path lengths, compatibility with CMOS fabrication and the elimination of vertical alignment and packaging issues. Moreover, the ultra‐compact and ultra‐broadband operation of 2P‐NA HVC are attractive for ultra‐broadband biophotonic applications such as two‐photon fluorescence spectroscopy and surface‐enhanced coherent‐anti‐Stokes Raman spectroscopy [43, 44].…”

Section: Introductionmentioning

confidence: 99%

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Ultra‐compact and ultra‐broadband hybrid plasmonic‐photonic vertical coupler with high coupling efficiency, directivity, and polarisation extinction ratio

Pezeshki

Wright

Larkins

2022

IET Optoelectronics

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An ultra-compact, ultra-broadband vertical coupler for dense photonic integrated circuits is reported with a 1.07 � 0.62 μm 2 wavelength-scale footprint. This hybrid plasmonicphotonic coupler uses a unique two-plane plasmonic nanoantenna array on a siliconon-insulator waveguide. The in-and out-of-plane interference of the multipole moments and dual-feed nanoantennas results in efficient, unidirectional coupling. Finiteelement simulations show that, for a 0.8 μm diameter Gaussian beam, the maximum coupling efficiency (CE) is −3.4 dB across the telecommunication C-, L-and U-bands with a 3-dB bandwidth of 230 nm. The CE is > 9 dB higher than recently reported ultra-compact plasmonic couplers. The maximum directivity and polarisation extinction ratio across the C-to U-bands are 9.2 and 24.1 dB, respectively. Finally, as an out-coupler, it has a vertical directivity of >8.5 dB, enabling its use for vertical optical interconnects between two vertically separated circuits.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Ultra‐compact and ultra‐broadband hybrid plasmonic‐photonic vertical coupler with high coupling efficiency, directivity, and polarisation extinction ratio

Pezeshki

Wright

Larkins

2022

IET Optoelectronics

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“…To evaluate the effectiveness and overheads of the proposed IMSC, we implement it on a tailored 32-bit RISC processor [13,14] running on an ISA compatible with MIPS32. The RISC processor comes with a 6-stage pipeline, separate 4-way set-associative data and instruction caches, and memory management unit support for virtual memory.…”

Section: Discussionmentioning

confidence: 99%

IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions

Wang

Liu

Jiang

2022

IET Information Security

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A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be secretly introduced into the processor system as flaws or vulnerabilities. To address this problem that may cause potentially serious security breaches, the instruction set architecture (ISA) monitor and secure cache (IMSC) is proposed. As a lightweight solution, IMSC employs an ISA monitor to discover and correct any potential threats imposed by undocumented instructions, and it relies on a secure cache to ensure the credibility of the system. The authors’ case studies have confirmed that IMSC can effectively protect a processor system from being exploited by undocumented instructions and thus provide a trustworthy computing environment, all at low hardware and run‐time costs.

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Addition for Supercomputer Functionality

Stetsyura

2016

Communications in Computer and Information Science

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Heterogeneous 3-D circuits: Integrating free-space optics with CMOS

Cited by 8 publications

References 33 publications

Ultra‐compact and ultra‐broadband hybrid plasmonic‐photonic vertical coupler with high coupling efficiency, directivity, and polarisation extinction ratio

Ultra‐compact and ultra‐broadband hybrid plasmonic‐photonic vertical coupler with high coupling efficiency, directivity, and polarisation extinction ratio

IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions

Addition for Supercomputer Functionality

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