Heterogeneous chip multiprocessor architectures for big data applications

Abstract

Emerging big data analytics applications require a significant amount of server computational power. The costs of building and running a computing server to process big data and the capacity to which we can scale it are driven in large part by those computational resources. However, big data applications share many characteristics that are fundamentally different from traditional desktop, parallel, and scale-out applications. Big data analytics applications rely heavily on specific deep machine learning and data mining algorithms, and are running a complex and deep software stack with various components (e.g. Hadoop, Spark, MPI, Hbase, Impala, MySQL, Hive, Shark, Apache, and MangoDB) that are bound together with a runtime software system and interact significantly with I/O and OS, exhibiting high computational intensity, memory intensity, I/O intensity and control intensity. Current server designs, based on commodity homogeneous processors, will not be the most efficient in terms of performance/watt for this emerging class of applications. In other domains, heterogeneous architectures have emerged as a promising solution to enhance energy-efficiency by allowing each application to run on a core that matches resource needs more closely than a one-size-fits-all core. A heterogeneous architecture integrates cores with various micro-architectures and accelerators to provide more opportunity for efficient workload mapping. In this work, through methodical investigation of power and performance measurements, and comprehensive system level characterization, we demonstrate that a heterogeneous architecture combining high performance big and low power little cores is required for efficient big data analytics applications processing, and in particular in the presence of accelerators and near real-time performance constraints.

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

“…In recent years, many cores are trending as a on-chip computing platform [1]- [3] that can provide massive computational power for a heterogenous computing environment for big data [4] and other compute intensive embedded artificial intelligence applications [5]. Some recent work [6]- [9] on high performance computing for big data have focused on processing framework, architecture synthesis and utilization of multiple cores.…”

Nucleus

“…is la er e ect is commonly referred to as the breakdown of Dennard's scaling, which forces designs to operate only a fraction of the whole system, leaving the remaining design in a dark silicon state [8,10]. To address this, heterogeneous multiprocessors (HMPs) have emerged over other designs, especially in mobile devices [17,33], where keeping within a strict energy envelope while still being able to deliver performance on demand is crucial.…”

“…is la er e ect is commonly referred to as the breakdown of Dennard's scaling, which forces designs to operate only a fraction of the whole system, leaving the remaining design in a dark silicon state [8,10]. To address this, heterogeneous multiprocessors (HMPs) have emerged over other designs, especially in mobile devices [17,33], where keeping within a strict energy envelope while still being able to deliver performance on demand is crucial.To be able to deliver high performance through Memory Level Parallelism (MLP) and instruction level parallelism (ILP), an Out-of-Order (OoO) core is commonly used that has large caches, does aggressive speculation (branch predictors, prefetchers) and masks memory latency at the cost of signi cantly increased design complexity, area and power requirements. On the other hand, In-Order (InO) cores aim at conserving energy through a simpler and smaller design, at the expense of performance and lower operating frequency.…”

Efficient Pipelined Broadcast with Monitoring Processing Node Status on a Multi-Core Processor

“…The command indicates the root node; in this case, the root is P5. Therefore, all MPEs know the node number 2. The root MPE orders the local bus to distribute the value of the status register to all MPEs.…”