Heterogeneous High Performance Computer

Ross, V.W.

doi:10.1109/dodugc.2005.31

Cited by 3 publications

(4 citation statements)

References 3 publications

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“…Recent research proposed several high throughput and low latency Publish/Subscribe systems using multi-core processors [27] and heterogeneous hardware such as FPGA [52,55,40,38,41,45,44,37,24,50] and GPU [43,23,39].…”

Section: High Performance Event Processing In Publish/subscribe Systemsmentioning

confidence: 99%

Pub/Sub on stream

Zhao-ran

Chang

Xiang

et al. 2012

Proceedings of the 6th ACM International Conference on Distributed Event-Based Systems

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Publish/Subscribe (Pub/Sub) is becoming an increasingly popular message delivery technique in the Internet of Things (IoT) era. However, classical Publish/Subscribe is not suitable for some emerging IoT applications such as smart grid, transportation and sensor/actuator applications due to its lack of QoS capability.To meet the requirements for QoS in IoT message delivery, in this paper we propose the first Publish/Subscribe message broker with the ability to actively schedule computation resources to guarantee QoS requirements. We abstract the message matching algorithm into a task graph to express the data flow, forming a task-based stream matching framework. Based on the framework, we explore a message dispatching algorithm called Smart Dispatch and a task scheduling algorithm called DFGS to guarantee different QoS requirements.Experiments show that, the QoS-aware system can support more than 10x throughput than QoS-ignorant systems in representative Smart Grid cases. Also, our system shows near-linear scalability on a commodity multi-core machine.

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Section: High Performance Event Processing In Publish/subscribe Systemsmentioning

confidence: 99%

Pub/Sub on stream

Zhao-ran

Chang

Xiang

et al. 2012

Proceedings of the 6th ACM International Conference on Distributed Event-Based Systems

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“…This project aimed at exploiting the full range of resources available on the Heterogeneous High Performance Cluster (HHPC) at the Air Force Research Laboratory in Rome, NY [44]. Built by HPTi [26], the HHPC (seen in Figure 2.1) features a Beowulf via the PCI bus.…”

Section: Hpti Inc Hhpcmentioning

confidence: 99%

“…The HPTi HHPC From[44] cluster of48 heterogeneous computing nodes, where each node consists of a dual 2.2GHz Xeon PC running Linux and an Annapolis Microsystems WildStar II FPGA board.…”

mentioning

confidence: 99%

Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing

Cordes

Leeser

2009

EURASIP Journal on Embedded Systems

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First and foremost I owe many thanks to my advisor, Dr. Miriam Leeser, for her valuable technical guidance and support behind the scenes. Without her this project simply would not have been possible. Dr. Eric Miller made his extensive expertise with signal processing and radar algorithms available to me throughout the project, and assisted with gathering the information for Section 2.1. Al Conti, my fellow graduate student in the Reconfigurable Computing Laboratory, was a constant source of support and good cheer around the office. His assistance on the first implementation of the backprojection project provided the foundation for the work in this document. Finally, to my colleagues in the RCL, I express my heartfelt thanks for a friendly and enjoyable work environment and I wish them only the best in their future endeavors.

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“…For example, in 2003 AFRL Rome built a 48-node cluster of PCs with an off-the-shelf FPGA board on the PCI bus [24]. However, it is worth noting the difference between these style of clusters and the Adaptable Computing Cluster and the FPGA cluster described here.…”

Section: Related Workmentioning

confidence: 99%