Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding

Advanced Packaging and Heterogeneous Integration to Reboot Computing

“…An array of pillars with 5 µm diameter copper pillars was built on each chiplet and pillars on each pillar row was connected using a serpentine structure through the SiIF (shown in Figure 1(c)) to check for electrical continuity across the chiplet. Electrical tests on early test prototypes have shown >97% yield with low contact resistance of about 42 mΩ for 5 µm diameter copper pillars [16]. The average sheer strength of our metalmetal bonds was found to be higher than that of state-ofthe-art Sn-capped copper pillar bonds with annealing time of ~6 min.…”

“…The average sheer strength of our metalmetal bonds was found to be higher than that of state-ofthe-art Sn-capped copper pillar bonds with annealing time of ~6 min. More details regarding fabrication process steps of the SiIF substrate and metal-to-metal bonding used can be found in [16]. [16] (c) Serpentine test structure with 5 µm diameter pillar Figure 1(a) shows a schematic cross-section of SiIF based system assembly.…”

“…More details regarding fabrication process steps of the SiIF substrate and metal-to-metal bonding used can be found in [16]. [16] (c) Serpentine test structure with 5 µm diameter pillar Figure 1(a) shows a schematic cross-section of SiIF based system assembly. In Figure 1(b), we show the micro graph of multiple chiplets bonded on to an SiIF, where the chiplets are paced with inter-chiplet distance of 100 µm.…”

Integrated neural interfaces

“…Integrating four channels per Chiplet alleviates overhead from the bondpads, and facilitates assembly while offering a suitably fine-grained implementation. More aggressive fine-pitch bondpad schemes are possible with advanced processing techniques [23]. From a circuit perspective, potential limitations stem from parasitic capacitance incurred by bondpads, ESD diodes, and routing in the RDL.…”

“…The Chiplets are integrated with the microelectrode array through thermal compression flip-chip bonding [23], [24] onto redistribution layers (RDLs) on the backside of the array, which support chip-scale routing with low parasitics. The RDLs are fabricated with back-end-of-line techniques used for silicon interposers [22].…”