Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework

Gupta, Prakhar Raj; Visweswaran, G. S.; Narang, Gaurav; Grover, Anuj

doi:10.1109/socc.2016.7905494

Cited by 1 publication

(5 citation statements)

References 8 publications

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“…Based on a 28 nm technology, four implements were carried out for comparison: the traditional method, this paper method, Refs. [9,12] method. In all implements, the design was run to the post-route stage.…”

Section: Experiments and Resultsmentioning

confidence: 99%

“…Refs. [9,12] were not able to decrease the instance count because the memory bank configurations were nearly the same as with the traditional method.…”

Section: Glue Logic Area Sram Bank Areamentioning

confidence: 98%

“…The area of Ref. [9] was kept the same as the traditional method because it only considered the num_height x num_width bank array, which limited further optimization. The critical path delay decreased by 6.5%, also due to the use of LVT banks in the corner positions.…”

Section: Glue Logic Area Sram Bank Areamentioning

confidence: 99%

“…The total power and leakage power were both less than Refs. [9,12]. Finally, this co-optimization method was applied to different capacities (32~96 M bits) of memory subsystems to test its scalability.…”

Section: Glue Logic Area Sram Bank Areamentioning

confidence: 99%

“…Efficient memory bank integration methods have been implemented. Gupta et al proposed the use of heterogeneous memory banks to optimize the overall area of chips [9], while Yan et al proposed custom optimization techniques [10]. The second aspect is the optimization of memory bank placement.…”

Section: Introductionmentioning

confidence: 99%

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SRAM Compilation and Placement Co-Optimization for Memory Subsystems

Liu

2023

Electronics

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Co-optimization for memory bank compilation and placement was suggested as a way to improve performance and power and reduce the size of a memory subsystem. First, a multi-configuration SRAM compiler was realized that could generate memory banks with different PPA by splitting or merging, upsizing or downsizing, threshold swapping, and aspect ratio deformation. Then, a timing margin estimation method was proposed for the memory bank based on placed positions. Through an exhaustive enumeration of various configuration parameters under the constraint of timing margins, the best SRAM memory compilation configuration was found. This method could be integrated into the existing physical design flow. The experimental results showed that this method achieved up to an 11.1% power reduction and a 7.6% critical path delay reduction compared with the traditional design method.

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Section: Experiments and Resultsmentioning

confidence: 99%

“…Refs. [9,12] were not able to decrease the instance count because the memory bank configurations were nearly the same as with the traditional method.…”

Section: Glue Logic Area Sram Bank Areamentioning

confidence: 98%

Section: Glue Logic Area Sram Bank Areamentioning

confidence: 99%

Section: Glue Logic Area Sram Bank Areamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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