Heterogeneous Memory Subsystem for Natural Graph Analytics

Addisie, Abraham; Kassa, Hiwot Tadese; Matthews, Opeoluwa; Bertacco, Valeria

doi:10.1109/iiswc.2018.8573480

Cited by 27 publications

(11 citation statements)

References 34 publications

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“…In fact, some of them may not be cached at all and need to be fetched from external memory. Experiments in [12] find that around 50% of the load requests in graph workloads result in cache misses. This leads to high variability in the load latency of these inputs, causing all the SIMD lanes to stall for the slowest input.…”

Section: B Challenges Due To Irregularitymentioning

confidence: 99%

DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm

Shah,

Olascoaga,

Zhao

et al. 2021

Preprint

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Computation in several real-world applications like probabilistic machine learning, sparse linear algebra, and robotic navigation, can be modeled as irregular directed acyclic graphs (DAGs). The irregular data dependencies in DAGs pose challenges to parallel execution on general-purpose CPUs and GPUs, resulting in severe under-utilization of the hardware. This paper proposes DPU, a specialized processor designed for the efficient execution of irregular DAGs. The DPU is equipped with parallel compute units that execute different subgraphs of a DAG independently. The compute units can synchronize within a cycle using a hardware-supported synchronization primitive, and communicate via an efficient interconnect to a global banked scratchpad. Furthermore, a precision-scalable posit TM arithmetic unit is developed to enable application-dependent precision. The DPU is taped-out in 28nm CMOS, achieving a speedup of 5.1× and 20.6× over state-of-the-art CPU and GPU implementations on DAGs of sparse linear algebra and probabilistic machine learning workloads. This performance is achieved while operating at a power budget of 0.23W, as opposed to 55W and 98W of the CPU and GPU, resulting in a peak efficiency of 538 GOPS/W with DPU, which is 1350× and 9000× higher than the CPU and GPU, respectively. Thus, with specialized architecture, DPU enables low-power execution of irregular DAG workloads.

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Section: B Challenges Due To Irregularitymentioning

confidence: 99%

DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm

Shah,

Olascoaga,

Zhao

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Prior work has proposed update batching techniques to improve the spatial locality of push algorithms. 1 Listing 1 shows pseudocode for a push version of PageRank 2 using update batching (UB). UB splits execution into two phases, binning and accumulation.…”

Section: Update Batchingmentioning

confidence: 99%

“…UB splits execution into two phases, binning and accumulation. In the binning phase, UB accesses the graph edges sequentially to generate the updates to destination 1 Though we adopt graph analytics terminology in this paper, we use the term update batching instead of the more common Propagation Blocking to avoid confusion with graph blocking/tiling, a different optimization [55,60] (Sec. 5).…”

Section: Update Batchingmentioning

confidence: 99%

“…OMEGA [1] proposes a hybrid cache subsystem where a scratchpad holds the most popular vertices (identified by degree-sorting the graph) and a conventional cache hierarchy serves requests for other data structures. A specialized unit near each scratchpad performs atomic updates on vertex data.…”

Section: Additional Related Workmentioning

confidence: 99%

“…PHI consists of three key techniques:(1) In-cache update buffering and coalescing extends caches to act as coalescing write buffers for partial updates. If the cache receives an update for a non-cached line, it does not fetch the line.…”

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confidence: 99%

See 2 more Smart Citations

Phi

Mukkara¹,

Beckmann²,

Sánchez³

2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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Many applications perform frequent scatter update operations to large data structures. For example, in push-style graph algorithms, processing each vertex requires updating the data of all its neighbors. Neighbors are often scattered over the whole graph, so these scatter updates have poor spatial and temporal locality. In current systems, scatter updates suffer high synchronization costs and high memory traffic. These drawbacks make push-style execution unattractive, and, when algorithms allow it, programmers gravitate towards pull-style implementations based on gather reads instead. We present PHI, a push cache hierarchy that makes scatter updates synchronization-and bandwidth-efficient. PHI adds support for pushing sparse, commutative updates from cores towards main memory. PHI adds simple compute logic at each cache level to buffer and coalesce these commutative updates throughout the hierarchy. This avoids synchronization, exploits temporal locality, and produces a load-balanced execution. Moreover, PHI exploits spatial locality by selectively deferring updates with poor spatial locality, batching them to achieve sequential main memory transfers. PHI is the first system to leverage both the temporal and spatial locality benefits of commutative scatter updates, some of which do not apply to gather reads. As a result, PHI not only makes push algorithms efficient, but makes them consistently faster than pull ones. We evaluate PHI on graph algorithms and other sparse applications processing large inputs. PHI improves performance by 4.7× on average (and by up to 11×), and reduces memory traffic by 2× (and by up to 5×). CCS CONCEPTS • Computer systems organization → Multicore architectures.

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