Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints

Abstract

Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor for computer systems so that we evaluate reliability of a task over various processor configurations. Next we build a mixed integer linear programming (MILP) model for minimizing chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors

“…Reliability issues such as a soft error and NBTI (negative bias temperature instability) have become matters of concern as a transistor pattern continues to shrink [9], [11]. Design for reliability (DFR) will become more and more important for space integrated circuits (ICs) as well as consumer ICs [13]- [17]. DFR techniques which achieve high reliability, small chip area, and low performance overhead are required for designing computer systems as traditional DFR techniques such as a multiplicating technique such as TMR (triple modular redundancy) are forbiddingly expensive.…”