Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement

Kwon, Taehyun; Imran, Muhammad; You, Jung Min; Yang, Joon-Sung

doi:10.23919/date.2018.8342272

Cited by 10 publications

(18 citation statements)

References 16 publications

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“…Compared to Level-0 and Level-3 data patterns, which use the smallest and largest resistance ranges, respectively, Level-1 and Level-2 patterns are much more likely to be impaired by resistance drift speed, as shown in Figure 2. In particular, the most error-vulnerable pattern (Level-2) suffers from four times more SER than the second most vulnerable pattern (Level-1) [8]. Several recent studies have suggested the allocation of a wider range of resistance to the most error-vulnerable data pattern in the 4LC PCM [13,27].…”

Section: Resistance Driftmentioning

confidence: 98%

“…Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.Electronics 2020, 9, 626 2 of 16 MLC PCM as the main memory or a storage class memory (SCM). Indeed, various methods have been introduced to use the MLC technology effectively when targeting PCM as the main memory [7][8][9][10][11][12][13][14][15].For reliable data retention, and for coping with the reduced sensing margin, iterative write-and-verify (read) operations must be executed for each memory cell in the MLC PCM, which deteriorates its lifetime and performance. In addition, MLC PCM suffers from a significantly higher soft error rate (SER) when compared to DRAM.…”

mentioning

confidence: 99%

“…In [10], the authors proposed an efficient scrubbing mechanism that could flexibly determine the scrubbing period considering the error-vulnerable patterns. In addition, recent studies focused on designing reliable 4LC PCM to mitigate the overhead caused by ECC and scrubbing, by expelling the most error-vulnerable pattern [7][8][9][10][11][12].Obviously, long ECC decoding latency is a significant bottleneck in achieving a high-performance memory system [17]. Moreover, complicated ECC algorithms are unacceptable in the MLC PCM based main memory considering its longer write latency than DRAM.…”

mentioning

confidence: 99%

“…Electronics 2020, 9, 626 2 of 16 MLC PCM as the main memory or a storage class memory (SCM). Indeed, various methods have been introduced to use the MLC technology effectively when targeting PCM as the main memory [7][8][9][10][11][12][13][14][15].…”

mentioning

confidence: 99%

mentioning

confidence: 99%

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Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

et al. 2020

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Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.Electronics 2020, 9, 626 2 of 16 MLC PCM as the main memory or a storage class memory (SCM). Indeed, various methods have been introduced to use the MLC technology effectively when targeting PCM as the main memory [7][8][9][10][11][12][13][14][15].For reliable data retention, and for coping with the reduced sensing margin, iterative write-and-verify (read) operations must be executed for each memory cell in the MLC PCM, which deteriorates its lifetime and performance. In addition, MLC PCM suffers from a significantly higher soft error rate (SER) when compared to DRAM. This is mainly caused by the resistance drift phenomenon that blurs the sensing boundary between adjacent states. The use of error-correction code (ECC) is a common technique in reducing the SER of MLC PCM; however, it adversely affects the performance and area efficiency.Scrubbing can help diminish the SER by reading, detecting, and correcting errors by utilizing the parity bit check and writing them back into the cell [16]. The shorter the scrubbing period, the lower the SER. However, frequent scrubbing accelerates the wearing out of PCM. In [10], the authors proposed an efficient scrubbing mechanism that could flexibly determine the scrubbing period considering the error-vulnerable patterns. In addition, recent studies focused on designing reliable 4LC PCM to mitigate the overhead caused by ECC and scrubbing, by expelling the most error-vulnerable pattern [7][8][9][10][11][12].Obviously, long ECC decoding latency is a significant bottleneck in achieving a high-performance memory system [17]. Moreover, complicated ECC algorithms are unacceptable in the MLC PCM based main memory ...

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Section: Resistance Driftmentioning

confidence: 98%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

et al. 2020

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Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

2020

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The existing charge-based memories like DRAM and flash are reaching their scaling limits. Phase change memory (PCM) is one of the most promising emerging memory technologies due to its good scalability and low leakage power. Multi-level cell (MLC) operation in PCM, which stores two or more bits in a single cell, is necessary to achieve a high storage density. However, a reduced resistance range in multiple storage levels of MLC PCM, introduces a lot of soft errors because of the resistance drift phenomenon. The poor reliability of MLC PCM requires strong error correction codes (ECC) which could severely degrade the storage density and performance. In this paper, we propose a cost-effective reliable MLC PCM architecture for improving MLC PCM reliability, storage density and performance. The proposed architecture exploits the data-dependent nature of resistance drift problem to reduce the ECC overhead. A simple state mapping is used to generate virtual data, which is half of the actual data size. ECC parity bits are generated based on virtual data bits instead of actual message bits, thus resulting in a reduced number of cells for parity bits. This improves the reliability and storage density of MLC PCM. The performance is also improved by minimizing the ECC overhead. Simulation results show an improvement of about 10 4 times in reliability and 10.9% in storage density compared to a conventional MLC PCM which uses a typical error correction scheme. Performance and energy efficiency are also improved up to 13.7% and 10%, respectively, by the proposed architecture. INDEX TERMS Emerging memories, phase change memory (PCM), MLC PCM, resistance drift, error correction code (ECC).

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Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density

Imran

Kwon

You

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement

Cited by 10 publications

References 16 publications

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density

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