Heterogeneously tagged caches for low-power embedded systems with virtual memory support

Zhou, Xian; Петров, П. П.

doi:10.1145/1344418.1344428

Cited by 9 publications

(6 citation statements)

References 23 publications

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“…Different from their work, we do not burden the hardware with the onus of ensuring correctness for static miss-speculation; neither do we require recompilation of application to take advantage of OVC. Zhou et al [39] proposed heterogeneously tagged (both virtual and physical tag) to allow cache access without TLB access for memory regions explicitly annotated by the application. Unlike their work, application modification is not necessary for OVC.…”

Section: L1mentioning

confidence: 99%

Reducing memory reference energy with opportunistic virtual caching

Basu

Hill

Swift

2012

SIGARCH Comput. Archit. News

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Section: L1mentioning

confidence: 99%

Reducing memory reference energy with opportunistic virtual caching

Basu

Hill

Swift

2012

SIGARCH Comput. Archit. News

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“…This approach reduces the number of DTLB accesses and thus DTLB energy usage, but L1D accesses occur as normal. Zhou et al propose a heterogenous tagged cache scheme, where the DTLB accesses for private data can be eliminated [18]. It requires to add some logic to the most significant bits of the calculated memory address which will go through the critical path of the DTLB.…”

Section: Related Workmentioning

confidence: 99%

Improving data access efficiency by using a tagless access buffer (TAB)

Bardizbanyan

Gavin²,

Whalley³

et al. 2013

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

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The need for energy efficiency continues to grow for many classes of processors, including those for which performance remains vital. Data cache is crucial for good performance, but it also represents a significant portion of the processor's energy expenditure. We describe the implementation and use of a tagless access buffer (TAB) that greatly improves data access energy efficiency while slightly improving performance. The compiler recognizes memory reference patterns within loops and allocates these references to a TAB. This combined hardware/software approach reduces energy usage by (1) replacing many level-one data cache (L1D) accesses with accesses to the smaller, more powerefficient TAB; (2) removing the need to perform tag checks or data translation lookaside buffer (DTLB) lookups for TAB accesses; and (3) reducing DTLB lookups when transferring data between the L1D and the TAB. Accesses to the TAB occur earlier in the pipeline, and data lines are prefetched from lower memory levels, which result in a small performance improvement. In addition, we can avoid many unnecessary block transfers between other memory hierarchy levels by characterizing how data in the TAB are used. With a combined size equal to that of a conventional 32-entry register file, a four-entry TAB eliminates 40% of L1D accesses and 42% of DTLB accesses, on average. This configuration reduces data-access related energy by 35% while simultaneously decreasing execution time by 3%.

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“…[22][23][24] focus on a low power cache organization. The tag reduction technique [5,[25][26][27][28] has received more attention in the literature because it can save energy of caches significantly. However previous research on tag reduction concentrates tag reduction on a single-core processor.…”

Section: Related Workmentioning

confidence: 99%

Energy Efficiency of a Multi-Core Processor by Tag Reduction

Zheng

Dong

Ota

et al. 2011

J. Comput. Sci. Technol.

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We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor.

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Heterogeneously tagged caches for low-power embedded systems with virtual memory support

Cited by 9 publications

References 23 publications

Reducing memory reference energy with opportunistic virtual caching

Reducing memory reference energy with opportunistic virtual caching

Improving data access efficiency by using a tagless access buffer (TAB)

Energy Efficiency of a Multi-Core Processor by Tag Reduction

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