Heuristic Analysis of Multiplierless Desensitized Half-Band Decimation Filter for Wireless Applications

Abstract

This paper elucidates the half-band FIR filter, which plays an important role when applying decimation by a factor of two. When the down-conversion is applied in sampling rate, this digital filter is frequently employed in conjunction with down-samplers. Despite the fact that numerous approaches have been proposed for designing half-band FIR filters, this paper proposes an utterly unique method for designing and implementing multiplierless half-band FIR filters, which minimizes the coefficient sensitivity and also reduces hardware complexity of the conventional half-band FIR filter. The proposed desensitized and further desensitized multiplierless half-band FIR filters are analyzed with four high-speed parallel prefix adders in Xilinx Vivado development tool and built on Kintex 7 FPGA for exploring power consumption, number of LUTs and delay. The proposed half-band structure is compared with the classical half-band architecture with respect to power consumption, path delay and number of LUTs. Based on the attained results on Kintex 7 FPGA, the proposed low-sensitivity filter structure outperforms with a 41.09% reduction in the number of LUTs, a 11.91% reduction in delay and a 38.35% reduction in power consumption in contrast to the existing desensitized half-band filter. Subsequently, the proposed further desensitized filter provides a 4.87% reduction in stopband ripple than the desensitized structure and an 8.84% reduction than the existing half-band decimation filter.