Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance

Silva-Filho, Abel G.; Cordeiro, Fernando; Sant'Anna, R. E.; Lima, Maria Luíza Carvalho de

doi:10.1007/11847083_8

Cited by 18 publications

(11 citation statements)

References 8 publications

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“…In [3], an automated method for adjusting two-level cache memory hierarchy in order to reduce energy consumption in embedded applications was presented. The proposed method, two-level cache exploration heuristic considering TECH-CYCLES method, make a small search in the space of configurations of the twolevel cache hierarchy, analyzing the impact of each parameter in terms of energy and number of cycles spent for a given application.…”

Section: Simulation and Estimation Methods: Overviewmentioning

confidence: 99%

Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems

Kroupis¹,

Soudris

2010

IFIP Advances in Information and Communication Technology

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A typical instruction memory design exploration process using simulation tools for various cache parameters is a rather time-consuming process, even for low complexity applications. In order to design a power efficient memory hierarchy of an embedded system, a huge number of system simulations are needed for all the different instruction memory hierarchies, because many cache memory parameters should be explored. Exhaustive search of design space using simulation is too slow procedure and needs hundreds of simulations to find the optimal cache configuration. This chapter provides fast and accurate estimates of a multi-level instruction memory hierarchy. Using a detail methodology for estimating the number of instruction cache misses of the instruction cache levels and power models; we estimate within a reasonable time the power consumption among these hierarchies. In order to automate the estimation procedure, a novel software tool named FICA implements the proposed methodology, which automatically estimates the total energy in instruction memory hierarchy and reports the optimal one.

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Section: Simulation and Estimation Methods: Overviewmentioning

confidence: 99%

Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems

Kroupis¹,

Soudris

2010

IFIP Advances in Information and Communication Technology

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“…Analisando-se hierarquia de memória com dois níveis, com segundo nível separado em cache de instrução e dados, Silva-Filho et al, propôs as heurísticas TECH-CYCLES [9] e TEMGA [10], onde a última foi baseada em algoritmos genéticos.…”

Section: Trabalhos Relacionadosunclassified

NSGAII Applied to Unified Second Level Cache Memory Hierarchy Tuning Aiming Energy and Performance Optimization

Cordeiro

Silva-Filho

2010

2010 11th Symposium on Computing Systems

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The evolutionary algorithm NSGAII was applied to the problem of cache memory hierarchy optimization, considering unified second level. The proposed multiobjective approach considers two main objectives: energy consumption and performance related to the number of cycles necessary to run an application.Experiments done with 18 applications from two benchmarks (PowerStone and Mibench) permitted to conclude that found solutions, when NSGAII is applied, are close to optimal solutions. Results also were compared with an existing heuristic (TECH-CYCLES) and was observed that the quality of results obtained are superior in all analyzed cases, being in average 187 times lower in terms of the cost function (FC=Energy x Cycles) that represents the two components: energy and cycles of the application. Evaluating the impact in terms of number of simulations and obtained results, could be noticed that NSGAII needs only 1% of search space, becoming competitive for architecture exploration with unified second level.

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“…After that, Silva-Filho et al also proposed some optimization mechanisms for two-level caches: TECH [5], TECH-CYCLES [6] and TEMGA [7]. The former indicates that the order of exploration of the cache parameters can have a considerable impact in the energy saving.…”

Section: Introductionmentioning

confidence: 97%

A methodology for tuning two-level cache hierarchy considering energy and performance

Silva-Filho

Araujo

2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

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In this paper we propose a hybrid methodology for tuning both instruction and data cache configurations in a two-level memory hierarchy. The method aims to minimize energy consumption without compromise the performance. It combines two optimization mechanisms in order improve energy and performance results without increasing the configuration space. Experiments based on simulations were performed for 12 applications from the Mibench suite benchmark and the proposed methodology achieved better efficiency in 60% of the evaluated cases compared with existing heuristics.

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Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance

Cited by 18 publications

References 8 publications

Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems

Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems

NSGAII Applied to Unified Second Level Cache Memory Hierarchy Tuning Aiming Energy and Performance Optimization

A methodology for tuning two-level cache hierarchy considering energy and performance

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