HEVC Decoder Analysis on ARM Processor

Ayadi, Lella Aicha; Damak, Tarak; Loukil, Hassen; Ayed, Mohamed Ali Ben; Nouri, Mohammad

doi:10.1109/ssd.2018.8570668

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…The authors saved 49ś52% of the encoding time at a 0.60ś0.88% BD-Rate increase. Another acceleration strategy is to oload the full inter prediction step, or a part of it, to a GPU [53,58,134] or an FPGA [10,12]. A comprehensive review by Zhang et al [164] covers literature on inter prediction of HEVC up to the year 2019.…”

Section: Computational Complexity Analysismentioning

confidence: 99%

Image and Video Coding Techniques for Ultra-low Latency

et al. 2022

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The next generation of wireless networks fosters the adoption of latency-critical applications such as XR, connected industry, or autonomous driving. This survey gathers implementation aspects of different image and video coding schemes and discusses their tradeoffs. Standardized video coding technologies such as HEVC or VVC provide a high compression ratio, but their enormous complexity sets the scene for alternative approaches like still image, mezzanine, or texture compression in scenarios with tight resource or latency constraints. Regardless of the coding scheme, we found inter-device memory transfers and the lack of sub-frame coding as limitations of current full-system and software-programmable implementations.

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Section: Computational Complexity Analysismentioning

confidence: 99%

Image and Video Coding Techniques for Ultra-low Latency

et al. 2022

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“…A complexity and performance profiling of HEVC standard should be considered to identify the most computationally expensive tasks and to pinpoint the critical code parts, candidate for a more optimization of the algorithm. In that regard, different works were performed to provide the profiling of HM, 1 the software reference of HEVC on both standard processor (Intel Core), 18 or on ARM processors 19‐21 for the encoder and decoder process. Before releasing the HW/SW HM16.7 implementation, a performance timing analysis of HM16.7 was also performed on Zynq MP platform using “Gprof” GNU profiler 22 in order to have a clearer and more accurate analysis results of HEVC on Zynq MP platform, by giving the total execution time spent on this heterogeneous platform for each function.…”

Section: Proposed Hardware Architecturementioning

confidence: 99%

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

Touzani

Mansouri

Errahimi

et al. 2021

Circuit Theory & Apps

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Summary Statistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%).

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“…Recently, the international telecommunications union (ITU) introduced high-efficiency video coding (HEVC) [2][3][4] as the next-generation video compression standard. Compared with its predecessor (MPEG-4 AVC/H.264), it presents about twice the compression efficiency without deteriorating the quality level of the encoded signals [5,6].…”

Section: Introductionmentioning

confidence: 99%

Hardware Update through Digital TV Signals

et al. 2021

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This paper presents a new hardware reconfiguration approach named hardware reconfiguration through digital television (HARD), which can update FPGA hardware modules based on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams) signaled and broadcast through open DTV signals via data streaming to be identified, acquired, decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers. Service information content, specially designed for identifying and describing the characteristics of multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary information in the traditional DTV style. The receiver framework, in turn, checked whether those characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments performed with an implementation of the proposed methodology confirmed its feasibility and showed that remounting and reconfiguration times were satisfactory and presented no blocking aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices, minimize device costs in the long term, and provide better hardware reuse.

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HEVC Decoder Analysis on ARM Processor

Cited by 4 publications

References 5 publications

Image and Video Coding Techniques for Ultra-low Latency

Image and Video Coding Techniques for Ultra-low Latency

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

Hardware Update through Digital TV Signals

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