Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs

Abstract

Modern Graphics Processing Units (GPUs) require large hardware resources for massive parallel thread executions. In particular, modern GPUs have a large register file composed of Static Random Access Memory (SRAM). Due to the high leakage current of SRAM, the register file consumes approximately 20% of the total GPU energy. The energy efficiency of the register file becomes more critical as the throughput of GPUs increases. For more energy-efficient GPUs, the usage of non-volatile memory such as Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as the GPU register file has been studied extensively. STT-MRAM requires a lower leakage current compared to SRAM and provides an appropriate read performance. However, using STT-MRAM directly in the GPU register file causes problems in performance and endurance because of complicated write procedures and material characteristics. To overcome these challenges, we propose a novel register file architecture and its management system for GPUs, named Hi-End, which exploits the data locality and compressibility of the register file. For STT-MRAM-based GPU register files, Hi-End increases the data write performance and endurance by caching and data compression, respectively. In our evaluation, Hi-End enhances the energy efficiency of a GPU register file by 70.02% and reduces the write operations by up to 95.98% with negligible performance degradation compared to SRAM-based register files.INDEX TERMS Graphics processing unit, register file, spin-transfer torque magnetic random access memory, data compression, energy efficiency, endurance, chip area.

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

“…Also, they adopted a write buffer scheme to hide long write latency for MRAM, which is widely used in many other previous work on MRAM-based on-chip caches [ [41]. In addition to MRAM-based large caches, several researchers proposed MRAM-based register files [17] and L1 caches [20] [36], which also avoid long MRAM write latency based on small write buffers.…”

TEA-RC: Thread Context-Aware Register Cache for GPUs

“…Among the various components in GPUs, the register file is one of the most powerhungry components, consuming around 15-20% of total GPU energy [9]- [13]. Over the past decade, researchers have explored several architectural techniques to minimize the energy consumption of the GPU register file [9]- [11], [14]- [18]. One attractive solution to minimize the energy consumption of the register file is to adopt emerging nonvolatile memories (NVMs) -such as spin-transfer torque magnetoresistive random access memory (STT-MRAM) and spin-orbit torque MRAM (SOT-MRAM) [11], [14], [16] -as a substitute for static random-access memory (SRAM) of an existing register file.…”

“…Over the past decade, researchers have explored several architectural techniques to minimize the energy consumption of the GPU register file [9]- [11], [14]- [18]. One attractive solution to minimize the energy consumption of the register file is to adopt emerging nonvolatile memories (NVMs) -such as spin-transfer torque magnetoresistive random access memory (STT-MRAM) and spin-orbit torque MRAM (SOT-MRAM) [11], [14], [16] -as a substitute for static random-access memory (SRAM) of an existing register file. Leveraging their low leakage power, implementing the register file using NVMs significantly reduces the leakage energy consumption.…”

RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU

“…El banco de registros es una de las estructuras de memoria que más energía consume en una GPU, siendo responsable de aproximadamente un 20 % del consumo total de energía del dispositivo [9] y su consumo aumenta generación tras generación. Por ejemplo, el banco de registros de NVIDIA Tesla V100, con 20 MB, es 5 veces más grande que su homólogo en Tesla K40 [19].…”