Hierarchical memories: Simulating quantum LDPC codes with local gates

Abstract

Constant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family of N, K, D codes, referred to as hierarchical codes, that encode a number of logical qubits K = Ω(N/ log(N ) 2 ). The N th element H N of this code family is obtained by concatenating a constant-rate quantum LDPC code with a surface code; nearest-neighbor gates in two dimensions are sufficient to implement the syndrome-extraction circuit C H N and achieve a threshold. Below threshold the logical failure rate vanishes superpolynomially as a function of the distance D(N ). We present a bilayer architecture for implementing C H N , and estimate the logical failure rate for this architecture. Under conservative assumptions, we find that the hierarchical code outperforms the basic encoding where all logical qubits are encoded in the surface code.