Hierarchical System Design Using Refinable Recursive Petri Net

Bouneb, Messaouda; Saïdouni, Djamel Eddine

doi:10.4149/cai_2018_3_635

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Cited by 2 publications

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“…Besides the formal translation and the timing consideration, we investigate the parallel execution specification. For this purpose, the true-concurrency semantics based DTPN model is used to obtain durational action Timed Automata (daTA) (semantics representation) [42,43]. In daTA, both true concurrency and action duration are considered.…”

Section: Formalisationmentioning

confidence: 99%

Formal Verification of UML MARTE Specifications Based on a True Concurrency Real Time Model

Chabbat

Saïdouni

Boukharrou

et al. 2020

cai

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For critical embedded systems the formal validation and verification is required. However, the real-time model checking suffers from problems of statespace explosion and clock explosion. The aim of this paper is to ensure an improvement of the Modeling and Analysis of Real-Time Embedded systems (MARTE), which is de facto standard, with formal semantics for verification finality. Therefore, we propose an operational method for translating UML sequence diagrams with MARTE annotations to Time Petri nets with Action Duration specifications (DTPN). Based on true concurrency semantics, the semantics of these specifications are defined in terms of Duration Action Timed Automata (daTA).

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Section: Formalisationmentioning

confidence: 99%