High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse

Abstract

This paper describes an application-specific instruction set for a configurable processor to accelerate motion-compensated frame rate conversion (MC-FRC) algorithms based on block motion estimation (BME). The paper shows that the key to achieve very high performance when creating new instructions is to leverage, at the same time, parallel computations, data reuse, and efficient cache use. This is supported by concrete examples that demonstrate how it can be done in the case of the two algorithms considered. The new instructions are used to implement two BME algorithms: one implements the full search (FS) block matching algorithm (BMA), while the other implements the One-Dimensional Full Search (ODFS) BMA. The obtained acceleration factors exceed one hundred for the MC-FRC algorithm embedding the FS algorithm and twenty for the ODFS algorithm. The results show that getting such global acceleration is the consequence of combining parallel computations, data reuse, and efficient cache use, not of only one of them.

Estimation of energy performance in computing platforms

“…The extended instruction-set developed to accelerate MC-FRC was described in detail in [10]. Fourteen application-specific instructions created for the MC-FRC algorithm increase the processor power by 72% (P o ).…”