High accuracy stimulus generation for A/D converter BIST

Abstract

A novel approach is presented for digital generation of an analog waveform suitable f o r BIST of high-resolution analog-to-digital converters (ADCs). The staircase-like exponential waveform is shown to have propenies of a perfectly linear ramp when used as the stimulus f a r a 3" order polynomial Jitting algoriihm that measures offset, gain, 2" and 3d harmonic distonion. The technique is particularly suitable f o r iesting high resolution ( > I 2 bits) sigma-delta ADCs in a noisy environment, which can then be used to test digital-toanalog converters (DACs). Experimental results for a 44 kHz I b b i t ADC show, that the technique measures distoriion with better than 0.01% accuracy in the presence of random and 50 o r 60 Hz noise. IntroductionMore than 60% of IC designs now include mixedsignal circuitry [l], typically an ADC or DAC, or both. These converters are typically 8-12 bits, however 16-bit converters are common, especially for audio frequencies.Sigma-delta techniques allow this resolution to be practical in a CMOS process that achieves 0.1 % element matching at best, and the converter is almost routinely integrated alongside large amounts of high frequency digital circuitry.In this context, the testing of these components becomes a problem mainly because of noise in a production environment, and test time. Also, high pincount mixed-signal testers typically cost 2 5 4 0 % more than digital testers. Connecting the ADC to an external mixed-signal tester requires a careful loadboard layout to limit noise and to provide higher precisiodresolution than the ADC under test. The problem is worse when testing an ADC on a bench-top, in a system, or in the fieldpower line noise inevitably corrupts low-level measurement results.In telecom applications, the sampling interval is always chosen to be a multiple of the power line frequency (60 Hz in some countries, 50 Hz in others) [7], hut this has not been a consideration for previously published BIST.A built-in-self test (BIST) technique for ADCs capable of evaluating key performance parameters is one way to alleviate these problems. A purely digital interface between the BIST circuitry and the tester allows a lower cost, digital tester to perform the test. A small amount of analog circuitry on the loadboard is feasible in close proximity to the chip, as long as it does not need to be accurate or bulky.One of the main challenges of developing any mixed-signal BIST technique is the generation of a stimulus waveform with predictable and controllable characteristics. For the technique presented in this paper, the ideal waveform would be a linear ramp with a controlled slope.The linearity required must be significantly better than the resolution of the ADC under test.To qualify as a BIST technique, the stimulus must be self-generated. Using on-chip analog circuitry to generate the ramp is often not practical because it needs custom layout or redesign for every technology in which the BIST circuit is to be implemented. For ASIC or FPGA design, mask-level layout by the custom...

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems

“…In [8][9], one exponential obtained by the discharge of a capacitor is proposed as a modification of the classical histogram technique. On the other hand, [10] uses a staircase-like exponential instead of a linear ramp and, through a polynomial fitting algorithm, provides a test method adequate for BIST.…”

Flexible embedded test solution for high-speed analogue front-end architectures

“…BIST techniques for static performance parameter evaluation have been published based on the feedback loop methodology [22] and histogram testing [23,24]. A BIST technique targeting high-resolution converters is published in [25,26], where a polynomial fitting algorithm is employed to the converter's ramp response to determine gain error, offset error, and secondand third-order harmonics.…”

ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus

“…The new set-up of the ramp generator can test an ADC up to 14 bits. In [9], a staircase-like exponential waveform is used as the test input signal; it is generated by a pulse-width modulation (PWM) signal followed by an off-chip RC filter. With this method, the 3rd harmonic distortion of an ADC up to 20-bits can be tested with a 3rd order polynomial fitting algorithm.…”