2020
DOI: 10.35848/1347-4065/ab75b8
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High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

Abstract: A feasibility study has been carried out to find an alternative method to the laborious cum expensive physical vapor deposition (PVD)/atomic layer deposition for the deposition of barrier and seed metal layers inside the deep Si trenches with aspect ratio (AR) greater than 10, by using low-cost, highly-scalable, CMOS-compatible electroless (EL) plating method to plate Ni as (barrier cum) seed layer for the fabrication of sub-μm as well as 10 μm width copper through-silicon-vias (Cu-TSVs). Micro-structural data… Show more

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Cited by 10 publications
(3 citation statements)
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“…The TNT process does not involve any metallization process, and is capable of fabricating on 300 mm wafers, dramatically increasing the production volume compared to 100 mm wafers employed in academic settings. Furthermore, high aspect ratio etching technologies are well established and are employed in current productions, such as through-silicon-via (TSV) in 3D LSI integration and 3D capacitors in DRAM [ 82 , 83 ]. Therefore, TNT Si chips can be manufactured in semiconductor foundries using the standard semiconductor process, enabling high-volume mass production for potential future commercialization.…”
Section: Challenge and Future Prospectsmentioning
confidence: 99%
“…The TNT process does not involve any metallization process, and is capable of fabricating on 300 mm wafers, dramatically increasing the production volume compared to 100 mm wafers employed in academic settings. Furthermore, high aspect ratio etching technologies are well established and are employed in current productions, such as through-silicon-via (TSV) in 3D LSI integration and 3D capacitors in DRAM [ 82 , 83 ]. Therefore, TNT Si chips can be manufactured in semiconductor foundries using the standard semiconductor process, enabling high-volume mass production for potential future commercialization.…”
Section: Challenge and Future Prospectsmentioning
confidence: 99%
“…To eliminate copper diffusion into silicon, a barrier layer of TiN, TiW, TaN, CoP, CoNiP or NiP is applied to the TSV walls [ 14 , 15 , 16 , 17 ]. Copper deposition in TSVs is undertaken by electroplating, which entails the deposition of a seed layer [ 18 ]. Usually, barrier and seed layers are deposited by sputtering; however, as the aspect ratio (AR) of TSV increases, this method does not achieve the desired results in the conformal coatings.…”
Section: Introductionmentioning
confidence: 99%
“…Copper deposition in TSVs is undertaken by electroplating, which entails the deposition of a seed layer [18]. Usually, barrier and seed layers are deposited by sputtering; however, as the aspect ratio (AR) of TSV increases, this method does not achieve the desired results in the conformal coatings.…”
Section: Introductionmentioning
confidence: 99%