High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

Abstract

Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (> 8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications. IntroductionDuring the past decades, hybrid integration of IC and MEMS technology has been dominated by 2-D approaches, resulting in Multi-Chip Modules (MCM) where different dies are integrated on a single substrate, and System-on-Chip (SoC) solutions where different functionalities are merged onto one die. CMOS and MEMS processing are both well-established and cost-efficient base technologies that are characterized by short development times, low fabrication costs and high yields. Separate manufacturing of CMOS integrated circuit dies and MEMS dies and their subsequent integration into a System-in-Package (SiP) offers high versatility and low process costs, and thus is an attractive alternative to SoC solutions. Especially 3D-integrated System in Package (3D-SiP) solutions, which are based on vertical chip stacking, are a general trend in many integration approaches. Not only do 3D-SiPs decrease costs by reducing the volume and weight of the package, but they also improve system performance through enhanced signal transmission speed and lower power consumption which is of importance for various demanding applications [1,2]. This is due primarily to the shorter signal path lengths and lower capacitive, resistive and inductive parasitic components that are enabled by TSVs [3]. 3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers. Large development efforts for the realization of reliable and cost-efficient TSVs are currently ongoing and the first commercially available devices such as MEMS inertial sensors and microphones, CMOS imagers and power LEDs successfully incorporate TSV technology [4][5][6].

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

“…For through-vias with large diameters, it is also possible to use Ni wire bonding and BCB filling to fabricate the conductors and insulators [133]. Additionally, commercially-available ferromagnetic Ni wires have been employed to fill TSVs with diameters down to 35 μm, using an external magnetic-field-assisted selfassembly method [134], [135]. Carbon nanotube (CNT) bundles grown by LPCVD have also been demonstrated as TSV conductors [136], but the high temperatures required for CNT growth and the large interfacial resistance between CNTs and metal contact pads still represent challenges.…”

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

“…The proposed fabrication method enables a cost-effective fabrication of high aspect ratio TSVs especially for low-to medium-I/O density applications such as interposers and MEMS. A proof of concept of the fabrication of TSVs with an aspect ratio of 8 by manual magnetic assembly has been shown by the authors earlier [18,19]. This method has also been adopted for the assembly of SMD capacitors into through-silicon holes [42].…”

“…Chemical vapor deposition (CVD) is a well-established CMOS-compatible process with moderate temperature requirements [1,2,11,9] and is therefore the most commonly used method for a direct deposition of silicon dioxide or silicon nitride on via sidewalls. Organic dielectrics [16,17] including benzocyclobutene (BCB) [13,15,18,19], epoxy-based polymers [13,12], silicone [13] or Parylene [11] are used as well. Polymers, especially low-k types with a lower relative permittivity compared to silicon dioxide, are very attractive for the realization of TSVs with improved electrical characteristics in terms of lower capacitive parasitics [20,12,15].…”

Harmonized Rapid Prototyping of Millimeter-Wave Components Using Additive and Subtractive Manufacturing

“…The method of rapid prototyping HSIW-based millimeter-wave components using a combination of additive and subtractive manufacturing processes has proved effective. The proposed technique has advantages in the ease of design, low fabrication and material cost, requires no chemical processing, and can be used to realize a new class of microwave and millimeter-wave components with the possibility of conformal and flexible structures [43]. However, this method was necessary for fabricating the prototype components for testing the performance before considering mass production.…”