High Data Rate DMT SERDES Design

Abstract

The research presented in this thesis involves implementing a high data rate wireline communication system using Discrete Multitone (DMT) transmission. A theoretical analysis of the model of channels typically used for serializer/deserializer SERDES chip-to-chip communication is done, showing the benefits of DMT through improved spectral efficiency, and simplified transceiver design due to the pseudo-narrowband characteristics of DMT. Simulations results demonstrate this benefit by being able to achieve higher data rates than conventionally used non-return-to-zero (NRZ) and pulse-amplitude modulation (PAM) typically used, even with typical channel correction circuitry such as continuous-time linear equalizers (fs) and decision-feedback equalizers (DFEs). Furthermore, a combined bit-loading/power allocation and transmit side equalization algorithm is presented that can improve the data rate of the system and decrease its bit error rate. Measurement results are demonstrated using a digital-to-analog-converter (DAC) and analog-to-digital converter (ADC) test bed in realistic conditions for chip-to-chip communications with a data rate over 250 GB/s with a sufficient overhead for forward-error-correction (FEC) coding needed to reduce the bit-error rate (BER).

Next-Generation O-Band Coherent Transmission for 1.6 Tbps 10 km Intra-Datacenter Interconnects

“…That DAC has an output swing of 1 Vpp and consumes 432 mW.  We assume the DAC power consumption scales linearly with the sampling rate as in [20].  For calculations, we assume that the overall power consumption of this transmitter to be 600 mW, where the digital DSP blocks consumes 170 mW, and the analog part consumes the remaining 430 mW.…”