High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

Abstract

In this paper, we present a high-density fourtransistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted -silicon on insulator MOS transistors to show the compatibility between the 4T SRAM and the 3-D design and the considerable density gain that they can achieve when combined. The 4T SRAM bitcell has been characterized to investigate the critical operations in terms of stability (retention and read) taking into account the postlayout parasitic elements. Thus, failure mechanisms are exposed and explained. Based on this paper, a data-dependent dynamic back-biasing scheme improving the bitcell stability is developed. A specific read-assist circuit is also proposed in order to enable a large number of bitcells per column in a memory array. Finally, the designed bitcell offers up to 30% area gain compared to a planar six-transistor SRAM bitcell in the same technology node.

Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28nm 3D CoolCubeTM Technology

“…Therefore, to enhance the retention stability, the VT gap between the NMOS and PMOS is enlarged by 120 mV (+60 mV PMOS VT, −60 mV NMOS VT). This optimal balance between NMOS and PMOS VT is achievable using the available process tuning handles as demonstrated with silicon measurements in 14 nm FDSOI [7].…”

“…Since the reliability of read operation is assured by adding a read port with row based VGND, the 4T core of the bitcell can be optimized only for best balance between retention and write stability. The mechanism of retention in the 4T bitcell relies on the equilibrium of the leakage current present in the bitcell, as detailed in previous works [6] [7].…”

“…Based on previously published work [6] [7][8], we propose a 4T-based SRAM bitcell further optimized for ULV operation, particularly for energy-efficient write operation. Moreover, we propose to use a dedicated read port coupled to a VGND [9] to improve even more the performance of read operation.…”

Blade

“…In particular, DRC 2 's architecture deviates significantly from typical cache structure as it utilizes 10T SRAM cells and complex periphery for maximum performance, resulting in what is more an accelerator than a cache. Alternatively, the ultra low voltage (0.3V) iSC architecture presented in [11] relies on unconventional CMOS technology (deeply depleted channel) and modified 4T bitcells, known to suffer from stability issues [9] and disturb risks, as well as showing poor performance with voltage scaling (100Mhz@0.6V).…”

A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors

“…integration, along with its miniaturesized inter-layer vias, enables significant area savings and interconnect delay reduction for integrated circuits and systems [1]. As far as the applications of this technology are concerned, the research focus has been mainly with the area, performance and power gains of M3D digital systems [2]- [4]. Recently, applications of Monolithic 3-D (M3D) integration in radio frequency/analog mixed-signal (RF/AMS) circuits and systems have been proposed as well [5].…”