High density and low-cost silicon interposer using thin-film and organic lamination processes

Yook, Jong‐Min; Kim, Jun Chul; Park, Sehoon; Ryu, Jong-In; Park, Jong Chul

doi:10.1109/ectc.2012.6248840

Cited by 22 publications

(6 citation statements)

References 3 publications

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“…A high-cost and performance-effective passive silicon interposer was reported by Yao S. et al [14]. A high-density and low-cost passive silicon interposer was proposed by Yook J.-M. et al [15]. The mismatch in CTE (coefficient of thermal expansion) among TSV's constituent materials will cause excess thermo-mechanical stress, which can eventually result in various reliability problems, such as open crack, interfacial delamination, and TSV protrusion [16,17].…”

Section: Silicon Interposer Productionmentioning

confidence: 99%

“…Cost Performance Reference 3D ASIC and memory integration 220/50 µm High A total of 3000 cycles with 10 min ramps and dwell from 0 to 100 • C [14] Passive Interposer 230/80 µm Low High density [15] RF wireless devices 120/60 µm N/A The loss of 0.6 dB/mm at 60 GHz. [22] Passive Interposer 130/50 µm N/A No electrical failure occurred in all samples after 500 MSTs (moisture sensitivity testing) and 1000 TCTs (thermal cycling testing from −40 • C to 125 • C).…”

Section: Application Via Depth/diametermentioning

confidence: 99%

“…[14] The interposer production A passive silicon interposer High density and low-cost. [15] The interposer production A passive silicon interposer with annular TSVs. The loss of 0.6 dB/mm at 60 GHz.…”

Section: Research Content Conclusion Referencementioning

confidence: 99%

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TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Tian

Liu

2018

Electronics

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Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.Electronics 2018, 7, 112 2 of 29 wafer was invented by M.G Smith et al. [2], which opposite surfaces were connected ohmically to the degenerately doped portions to be electrically connected along the thru-connection. With further research and exploration, 2.5D/3D integration technology with TSV realized integrated circuits with advantages of high interconnection density, high performance, low power consumption, and low cost [3,4]. In addition, the core is widely considered to be the leading technology in the field of high density packaging in the future and is an effective way to break through Moore's Law [5][6][7]. Figure 1. Silicon interposer through electrical copper coating technology production: (a) The construction of through-silicon via on the wafer; (b) The dry film etchant is stuck on the wafer, then exposed and etched; (c) Hole plating and pad fabrication by electroplating methods; (d) The photoresist removing. Adapted with permission from [27], Copyright Elsevier, 2016.

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Section: Silicon Interposer Productionmentioning

confidence: 99%

Section: Application Via Depth/diametermentioning

confidence: 99%

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TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Tian

Liu

2018

Electronics

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“…Based on the TSV fabrication process, slightly different coaxial-TSV fabrication techniques are developed [11,14,16]. Generally, the fabrication starts by etching deep via holes in the silicon substrate by wet or dry methods, including the laser drilling approach or the deep reactive ion etching (DRIE) method [17].…”

Section: Introductionmentioning

confidence: 99%

Electrical Characterization of Through-Silicon-via-Based Coaxial Line for High-Frequency 3D Integration (Invited Paper)

Zhao

Yuan

et al. 2022

Electronics

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Through-silicon-via (TSV)-based coaxial line techniques can reduce the high-frequency loss due to the low resistivity in the silicon substrate and thus can improve the efficiency of vertical signal transmission. Moreover, a TSV-based coaxial structure allows easily realizing the impedance matching in RF/microwave systems for excellent electrical performance. However, due to the limitations of existing available dielectric materials and the difficulties and challenges in the manufacturing process, ideal coaxial TSVs are not easy to obtain, and thus, the achieved electrical performance might be unexpected. In order to increase the flexibility of designing and manufacturing TSV-based coaxial structures and to better evaluate the fabricated devices, modeling and analysis theories of the corresponding high-frequency electrical performance are proposed in the paper. The theories are finally well validated using the finite-element simulation results, hereby providing guiding rules for selecting materials and improving manufacturing techniques in the practical process, so as to optimize the high-frequency performance of the TSV structures.

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“…This complicated fabrication process leads to high requirements for equipment, long process time, low yield and high cost. Many researchers have made a great effort to simplify the manufacturing process and reduce the cost [11][12][13][14]. However, few of these solutions could reduce the cost significantly while maintaining the performance and reliability.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

Luo

Wang

Sun

et al. 2018

J. Micromech. Microeng.

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The application of a Si interposer is hindered by its complicated manufacturing process, high cost and some reliability challenges such as through silicon via (TSV) leakage. In this paper, a fabrication approach using a Si interposer is proposed, which can simplify the manufacturing process significantly and reduce the cost by more than 40%. Benefiting from the simplified process, the TSV insulation layer stays intact during the whole manufacturing process, an ultra-low TSV leakage current can be obtained. To evaluate the performance and reliability of the interposer, test samples consisting of 136 TSVs are designed and fabricated. A series of tests are carried out to verify the electrical insulating performance and reliability of the interposer. Under the bias voltage of 5 V, the TSV leakage current is 2.05 × 10−14 A, which is much lower than the usual value in the range of 10−12–10−9 A. The yield of daisy chains exceeds 91.66% and that of individual TSVs is more than 99.91%. All the interposer samples have successfully passed the thermal cycle test, and the resistance variation of each individual pathway is within 5% after 200 cycles.

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High density and low-cost silicon interposer using thin-film and organic lamination processes

Cited by 22 publications

References 3 publications

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Electrical Characterization of Through-Silicon-via-Based Coaxial Line for High-Frequency 3D Integration (Invited Paper)

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

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